From 87f1e73494a62b4a7b5e7233d7954e5a7a9abf57 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 29 Nov 2018 07:08:57 +0000 Subject: [PATCH] get the predicate inv argument as well --- riscv/sv.cc | 5 +++++ riscv/sv_decode.h | 1 + 2 files changed, 6 insertions(+) diff --git a/riscv/sv.cc b/riscv/sv.cc index 25f9e54..946281a 100644 --- a/riscv/sv.cc +++ b/riscv/sv.cc @@ -213,6 +213,11 @@ reg_spec_t sv_insn_t::remap(uint64_t reg, bool intreg, int *voffs) * registers (i.e. XLEN bits). */ reg_t sv_insn_t::predicate(uint64_t reg, bool intreg, bool &zeroing) +{ + bool inv = false; + return predicate(reg, intreg, zeroing, inv); +} +reg_t sv_insn_t::predicate(uint64_t reg, bool intreg, bool &zeroing, bool &inv) { sv_reg_entry *pr = get_regentry(reg, intreg); if (!pr->active) diff --git a/riscv/sv_decode.h b/riscv/sv_decode.h index 0727487..9a0b76e 100644 --- a/riscv/sv_decode.h +++ b/riscv/sv_decode.h @@ -97,6 +97,7 @@ public: sv_reg_entry* get_regentry(uint64_t reg, bool isint); sv_pred_entry* get_predentry(uint64_t reg, bool isint); reg_t predicate(uint64_t reg, bool isint, bool &zeroing); + reg_t predicate(uint64_t reg, bool isint, bool &zeroing, bool &inv); void reset_vloop_check(void) { vloop_continue = false; } bool stop_vloop(void); -- 2.30.2