From 87f543be39b9e6f8b10ded67c182a1cfbde03a60 Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 8 Sep 2022 16:37:41 +0100 Subject: [PATCH] --- openpower/sv/rfc/ls001.mdwn | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn index cc22c2043..65fb4e507 100644 --- a/openpower/sv/rfc/ls001.mdwn +++ b/openpower/sv/rfc/ls001.mdwn @@ -137,6 +137,24 @@ Supercomputing ISAs. * Parallel Reduction REMAP, performs an automatic map-reduce using *any suitable scalar operation*. +# Scalar Operations. + +The primary reason for mentioning the additional Scalar operations is because +they are so numerous, with Power ISA not having advanced in the *general purpose* +compute area in the past 12 years, that some considerable care is needed. + +Summary: **to fit everything at least 75% of 3 Major Opcodes is required** + +Candidates include: + +* EXT006 (80% free) +* EXT017 (75% free but not recommended) +* EXT001 (50% free) +* EXT009 (100% free) +* EXT005 (100% free) +* brownfield space in EXT019 (25% but NOT recommended) + + [^extend]: Prefix opcode space **must** be reserved in advance to do so, in order to avoid the catastrophic binary-incompatibility mistake made by RISC-V RVV and ARM SVE/2 [^likeext001]: SVP64-Single is remarkably similar to the "bit 1" of EXT001 being set to indicate that the 64-bits is to be allocated in full to a new encoding, but in fact it still embeds v3.0 Scalar operations. [^pseudorewrite] elwidth overrides does however mean that all SFS / SFFS pseudocode will need rewriting to be in terms of XLEN. This has the indirect side-effect of automatically making a 32-bit Scalar Power ISA Specification possible, as well as a future 128-bit one (Cross-reference: RISC-V RV32 and RV128) -- 2.30.2