From 8813574d1d7b519e7e31efdfc8ea1f9948575c2f Mon Sep 17 00:00:00 2001 From: Yehowshua Date: Fri, 8 May 2020 19:05:44 +0100 Subject: [PATCH] --- 180nm_Oct2020/interfaces.mdwn | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/180nm_Oct2020/interfaces.mdwn b/180nm_Oct2020/interfaces.mdwn index dfd697c5b..1c83ebd97 100644 --- a/180nm_Oct2020/interfaces.mdwn +++ b/180nm_Oct2020/interfaces.mdwn @@ -21,22 +21,6 @@ Under consideration: # Secondary priorities -* a PLL (this is quite a lot however it turns the ASIC from a 24mhz -design into a 300mhz design) -* a TLB and MMU (in combination with a PLL if it is GNU/Linux OS -capable we have an actual viable *saleable product*, immediately) -* dual L1 Caches with the 2x 128-bit-wide L0CacheBuffer to merge 8x LD/STs -* multiple Common Data Buses to / from the RegFile along with a 4x -"Striped" HI/LO-32-ODD/EVEN access pattern. -* multi-issue -* PartitionedSignal-based integer pipelines -* an FP regfile and associated FP pipelines -* SV compliance -* 128x INT/FP registers -* GPU-style opcodes - Jacob you mentioned Texturisation opcodes as -being more important than e.g. SIN/COS. -* additional interfaces such as RGB/TTL, SDRAM, HyperRAM, RGMII, -SD/MMC, USB-ULPI * a pinmux TODO -- 2.30.2