From 8817b3c73fa879bd6fdb83220b56d1dea9d530ce Mon Sep 17 00:00:00 2001 From: Yehowshua Date: Fri, 8 May 2020 18:00:01 +0100 Subject: [PATCH] --- 180nm_Oct2020/interfaces.mdwn | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/180nm_Oct2020/interfaces.mdwn b/180nm_Oct2020/interfaces.mdwn index 685e3bdeb..d8747a37a 100644 --- a/180nm_Oct2020/interfaces.mdwn +++ b/180nm_Oct2020/interfaces.mdwn @@ -1,5 +1,7 @@ # Interfaces for the 180nm Oct2020 ASIC +http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-May/006355.html + Bugreport and discussion at These are bare minimum viability: @@ -19,4 +21,22 @@ Under consideration: # Secondary priorities +* a PLL (this is quite a lot however it turns the ASIC from a 24mhz +design into a 300mhz design) +* a TLB and MMU (in combination with a PLL if it is GNU/Linux OS +capable we have an actual viable *saleable product*, immediately) +* dual L1 Caches with the 2x 128-bit-wide L0CacheBuffer to merge 8x LD/STs +* multiple Common Data Buses to / from the RegFile along with a 4x +"Striped" HI/LO-32-ODD/EVEN access pattern. +* multi-issue +* PartitionedSignal-based integer pipelines +* an FP regfile and associated FP pipelines +* SV compliance +* 128x INT/FP registers +* GPU-style opcodes - Jacob you mentioned Texturisation opcodes as +being more important than e.g. SIN/COS. +* additional interfaces such as RGB/TTL, SDRAM, HyperRAM, RGMII, +SD/MMC, USB-ULPI +* a pinmux + TODO -- 2.30.2