From 8824d29454acf124f325420a02e4a4597a76ac9e Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 26 Sep 2018 06:28:32 +0100 Subject: [PATCH] include auto-generated identification of use of registers per op modified id_regs.py to take a single argument (file in riscv/insns to parse) added call to id_regs.py in riscv.mk.in included the auto-generated file in the insn_template.cc now each instruction has a way - BEFORE the emulated instruction is called - to identify which registers (RD, RS1-3, FRD, FRS1-3) are going to be used. --- id_regs.py | 7 +++++++ riscv/insn_template.cc | 1 + riscv/riscv.mk.in | 1 + 3 files changed, 9 insertions(+) diff --git a/id_regs.py b/id_regs.py index 5444355..3f5290d 100644 --- a/id_regs.py +++ b/id_regs.py @@ -19,9 +19,16 @@ """ import os +import sys insns_dir = "./riscv/insns" def list_insns(): + if len(sys.argv) == 2: + fullfname = sys.argv[1] + pth, fname = os.path.split(fullfname) + insn = fname[:-2] + return [(fullfname, insn)] + res = [] for fname in os.listdir(insns_dir): if not fname.endswith(".h"): diff --git a/riscv/insn_template.cc b/riscv/insn_template.cc index 9bfda57..61ec15f 100644 --- a/riscv/insn_template.cc +++ b/riscv/insn_template.cc @@ -22,6 +22,7 @@ #define INCLUDEFILE "insns/NAME.h" #define INSNCODE OPCODE #include "sv_decode.h" +#include "insns/regs_NAME.h" #define FN rv32_NAME #define ISASZ 32 #include "insn_template_sv.cc" diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in index 80755e7..c52d5c0 100644 --- a/riscv/riscv.mk.in +++ b/riscv/riscv.mk.in @@ -308,6 +308,7 @@ insn_list.h: $(src_dir)/riscv/riscv.mk.in $(riscv_gen_srcs): %.cc: insns/%.h insn_template.cc sed 's/NAME/$(subst .cc,,$@)/' $(src_dir)/riscv/insn_template.cc | sed 's/OPCODE/$(call get_opcode,$(src_dir)/riscv/encoding.h,$(subst .cc,,$@))/' > $@ + python id_regs.py $(src_dir)/riscv/insns/$(subst .cc,,$@).h riscv_junk = \ $(riscv_gen_srcs) \ -- 2.30.2