From 883cf527a5cf0fa84c5283ef3e797564b2332d50 Mon Sep 17 00:00:00 2001
From: "colepoirier@1ec9c8c87c85f09e4718cd80e0605065e33975f0"
 <colepoirier@1ec9c8c87c85f09e4718cd80e0605065e33975f0@web>
Date: Mon, 16 Nov 2020 17:51:19 +0000
Subject: [PATCH]

---
 HDL_workflow/ECP5_FPGA.mdwn | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/HDL_workflow/ECP5_FPGA.mdwn b/HDL_workflow/ECP5_FPGA.mdwn
index f6bc882fd..812252fbf 100644
--- a/HDL_workflow/ECP5_FPGA.mdwn
+++ b/HDL_workflow/ECP5_FPGA.mdwn
@@ -12,6 +12,13 @@ See https://bugs.libre-soc.org/show_bug.cgi?id=517#c0
 
 TODO checklist based on above
 
+<todo>
+Hello
+Motto
+Frodo
+Dodo
+</todo>
+
 ## Connecting the dots:
 
 Accurate render of board for reference <https://github.com/emard/ulx3s/blob/master/pic/ulx3st.jpg>
-- 
2.30.2