From 883ed108e443e7f9ea53fa13867a8ddf0ea9aea0 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Sat, 21 Oct 2006 17:19:33 -0700 Subject: [PATCH] Just give up if a store conditional misses completely in the cache (don't treat as normal write miss). --HG-- extra : convert_revision : c030eb6ba25318cae422e4da31e3b802049c8c74 --- src/mem/cache/cache_impl.hh | 27 ++++++++++++++++----------- 1 file changed, 16 insertions(+), 11 deletions(-) diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index 66a9ee554..64f658907 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -231,8 +231,11 @@ Cache::access(PacketPtr &pkt) exitSimLoop("A cache reached the maximum miss count"); } } - missQueue->handleMiss(pkt, size, curTick + hitLatency); -// return MA_CACHE_MISS; + + if (!(pkt->flags & SATISFIED)) { + missQueue->handleMiss(pkt, size, curTick + hitLatency); + } + return true; } @@ -585,7 +588,7 @@ Cache::probe(PacketPtr &pkt, bool update, assert(pkt->result == Packet::Success); } return 0; - } else if (!blk) { + } else if (!blk && !(pkt->flags & SATISFIED)) { // update the cache state and statistics if (mshr || !writes.empty()){ // Can't handle it, return pktuest unsatisfied. @@ -653,18 +656,20 @@ return 0; return memSidePort->sendAtomic(pkt); } } else { - // There was a cache hit. - // Handle writebacks if needed - while (!writebacks.empty()){ - memSidePort->sendAtomic(writebacks.front()); - writebacks.pop_front(); - } + if (blk) { + // There was a cache hit. + // Handle writebacks if needed + while (!writebacks.empty()){ + memSidePort->sendAtomic(writebacks.front()); + writebacks.pop_front(); + } - hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++; + hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++; + } return hitLatency; } - fatal("Probe not handled.\n"); + return 0; } -- 2.30.2