From 88500487e3a5292b0abd06bef0c118849e40f9a0 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 22 Jul 2020 22:11:57 +0100 Subject: [PATCH] re-add CRG (clock reset generator) --- src/soc/litex/sim.py | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/src/soc/litex/sim.py b/src/soc/litex/sim.py index 8707ba00..3c3dcbae 100644 --- a/src/soc/litex/sim.py +++ b/src/soc/litex/sim.py @@ -7,10 +7,9 @@ import os import argparse -from migen import ClockDomain - from litex.build.generic_platform import Pins, Subsignal from litex.build.sim import SimPlatform +from litex.build.io import CRG from litex.build.sim.config import SimConfig from litex.soc.integration.soc import SoCRegion @@ -76,11 +75,8 @@ class SoCSMP(SoCCore): self.platform.name = "sim" self.add_constant("SIM") - self.clock_domains.cd_sys = ClockDomain() - self.comb += [ - self.cd_sys.clk.eq(platform.request("sys_clk")), - self.cd_sys.rst.eq(platform.request("sys_rst")) - ] + # CRG ------------------------------------------------------- + self.submodules.crg = CRG(platform.request("sys_clk")) # SDRAM ---------------------------------------------------------- phy_settings = get_sdram_phy_settings( -- 2.30.2