From 886c5c58834ccdb5f54dfbcb7d09908dc102e20a Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 6 Jan 2020 10:23:04 -0800 Subject: [PATCH] write_xaiger: make more robust, update doc --- backends/aiger/xaiger.cc | 43 +++++++++++++--------------------------- 1 file changed, 14 insertions(+), 29 deletions(-) diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 1f1b9dffe..05e9678ee 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -847,17 +847,13 @@ struct XAigerWriter module->design->scratchpad_set_int("write_xaiger.num_outputs", output_bits.size()); } - void write_map(std::ostream &f, bool verbose_map) + void write_map(std::ostream &f) { dict input_lines; dict output_lines; - dict wire_lines; for (auto wire : module->wires()) { - //if (!verbose_map && wire->name[0] == '$') - // continue; - SigSpec sig = sigmap(wire); for (int i = 0; i < GetSize(wire); i++) @@ -875,14 +871,6 @@ struct XAigerWriter output_lines[o] += stringf("output %d %d %s %d\n", o - GetSize(co_bits), i, log_id(wire), init); continue; } - - if (verbose_map) { - if (aig_map.count(sig[i]) == 0) - continue; - - int a = aig_map.at(sig[i]); - wire_lines[a] += stringf("wire %d %d %s\n", a, i, log_id(wire)); - } } } @@ -899,10 +887,6 @@ struct XAigerWriter for (auto &it : output_lines) f << it.second; log_assert(output_lines.size() == output_bits.size()); - - wire_lines.sort(); - for (auto &it : wire_lines) - f << it.second; } }; @@ -914,8 +898,10 @@ struct XAigerBackend : public Backend { log("\n"); log(" write_xaiger [options] [filename]\n"); log("\n"); - log("Write the current design to an XAIGER file. The design must be flattened and\n"); - log("all unsupported cells will be converted into psuedo-inputs and pseudo-outputs.\n"); + log("Write the top module (according to the (* top *) attribute or if only one module\n"); + log("is currently selected) to an XAIGER file. Any non $_NOT_, $_AND_, $_ABC9_FF_, or"); + log("non (* abc9_box_id *) cells will be converted into psuedo-inputs and\n"); + log("pseudo-outputs.\n"); log("\n"); log(" -ascii\n"); log(" write ASCII version of AIGER format\n"); @@ -923,14 +909,10 @@ struct XAigerBackend : public Backend { log(" -map \n"); log(" write an extra file with port and box symbols\n"); log("\n"); - log(" -vmap \n"); - log(" like -map, but more verbose\n"); - log("\n"); } void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) YS_OVERRIDE { bool ascii_mode = false; - bool verbose_map = false; std::string map_filename; log_header(design, "Executing XAIGER backend.\n"); @@ -946,11 +928,6 @@ struct XAigerBackend : public Backend { map_filename = args[++argidx]; continue; } - if (map_filename.empty() && args[argidx] == "-vmap" && argidx+1 < args.size()) { - map_filename = args[++argidx]; - verbose_map = true; - continue; - } break; } extra_args(f, filename, args, argidx, !ascii_mode); @@ -960,6 +937,14 @@ struct XAigerBackend : public Backend { if (top_module == nullptr) log_error("Can't find top module in current design!\n"); + if (!design->selected_whole_module(top_module)) + log_cmd_error("Can't handle partially selected module %s!\n", log_id(top_module)); + + if (!top_module->processes.empty()) + log_error("Found unmapped processes in module %s: unmapped processes are not supported in XAIGER backend!\n", log_id(top_module)); + if (!top_module->memories.empty()) + log_error("Found unmapped memories in module %s: unmapped memories are not supported in XAIGER backend!\n", log_id(top_module)); + XAigerWriter writer(top_module); writer.write_aiger(*f, ascii_mode); @@ -968,7 +953,7 @@ struct XAigerBackend : public Backend { mapf.open(map_filename.c_str(), std::ofstream::trunc); if (mapf.fail()) log_error("Can't open file `%s' for writing: %s\n", map_filename.c_str(), strerror(errno)); - writer.write_map(mapf, verbose_map); + writer.write_map(mapf); } } } XAigerBackend; -- 2.30.2