From 88973c92a2d21a769ea61d0150c66c673d20bf9a Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 8 May 2022 22:52:05 +0100 Subject: [PATCH] --- openpower/sv/SimpleV_rationale.mdwn | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn index 161c5511e..c81a50425 100644 --- a/openpower/sv/SimpleV_rationale.mdwn +++ b/openpower/sv/SimpleV_rationale.mdwn @@ -892,8 +892,8 @@ the computation. In this case, that's an expensive inconvenience. Vertical-First allows *scalar* temporary registers to be utilised in the assessment as to whether a particular Vector element should be skipped, utilising a straight Branch instruction. This technique -is pioneered by Mitch Alsup and is a key feature of his VVM Engine -in MyISA 66000. Careful analysis of the registers within the +is pioneered by Mitch Alsup and is a key feature of his VVM Extension +to MyISA 66000. Careful analysis of the registers within the Vertical-First Loop allows a Multi-Issue Out-of-Order Engine to *amortise in-flight scalar looped operations into SIMD batches* as long as the loop is kept small enough to entirely fit into -- 2.30.2