From 889b2d55bb86177007d78cc2a9d232d0ff56cea6 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 11 Aug 2021 10:11:31 +0100
Subject: [PATCH] add (untested) TestRunner based on soc test_runner.py

---
 src/openpower/decoder/isa/test_caller.py | 76 ++++++++++++++++++++++++
 1 file changed, 76 insertions(+)

diff --git a/src/openpower/decoder/isa/test_caller.py b/src/openpower/decoder/isa/test_caller.py
index edc9c2bb..30c0fbe0 100644
--- a/src/openpower/decoder/isa/test_caller.py
+++ b/src/openpower/decoder/isa/test_caller.py
@@ -10,12 +10,88 @@ from openpower.decoder.isa.caller import ISACaller, inject
 from openpower.decoder.selectable_int import SelectableInt
 from openpower.decoder.orderedset import OrderedSet
 from openpower.decoder.isa.all import ISA
+from nmutil.formaltest import FHDLTestCase
 
 
 class Register:
     def __init__(self, num):
         self.num = num
 
+
+class TestRunner(FHDLTestCase):
+    def __init__(self, tst_data, include_fp=True):
+        super().__init__("run_all")
+        self.test_data = tst_data
+        self.include_fp = include_fp
+
+    def run_all(self):
+        m = Module()
+        comb = m.d.comb
+        instruction = Signal(32)
+
+        pdecode = create_pdecode(include_fp=self.include_fp)
+        m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
+
+        comb += pdecode2.dec.raw_opcode_in.eq(instruction)
+        sim = Simulator(m)
+
+        def process():
+
+            for test in self.test_data:
+
+                with self.subTest(test.name):
+                    generator = test.program
+
+                    gen = list(generator.generate_instructions())
+                    insncode = generator.assembly.splitlines()
+                    instructions = list(zip(gen, insncode))
+
+                    simulator = ISA(pdecode2, test.initial_regs,
+                                    test.initial_sprs,
+                                    test.initial_cr,
+                                    initial_insns=gen, respect_pc=True,
+                                    initial_svstate=test.svstate,
+                                    initial_mem=mem,
+                                    fpregfile=test.initial_fprs,
+                                    disassembly=insncode,
+                                    bigendian=0,
+                                    mmu=mmu)
+
+                    print ("GPRs")
+                    simulator.gpr.dump()
+                    print ("FPRs")
+                    simulator.fpr.dump()
+
+                    yield pdecode2.dec.bigendian.eq(0)  # little / big?
+                    pc = simulator.pc.CIA.value
+                    index = pc//4
+                    while index < len(instructions):
+                        print("instr pc", pc)
+                        try:
+                            yield from simulator.setup_one()
+                        except KeyError:  # instruction not in imem: stop
+                            break
+                        yield Settle()
+
+                        ins, code = instructions[index]
+                        print("    0x{:X}".format(ins & 0xffffffff))
+                        opname = code.split(' ')[0]
+                        print(code, opname)
+
+                        # ask the decoder to decode this binary data (endian'd)
+                        yield from simulator.execute_one()
+                        pc = simulator.pc.CIA.value
+                        index = pc//4
+
+        # run simulator multiple times, using the same PowerDecoder2,
+        # with multiple sub-tests
+        sim.add_process(process)
+        with sim.write_vcd("simulator.vcd", "simulator.gtkw",
+                           traces=[]):
+            sim.run()
+        return simulator
+
+
 def run_tst(generator, initial_regs, initial_sprs=None, svstate=0, mmu=False,
                                      initial_cr=0, mem=None,
                                      initial_fprs=None):
-- 
2.30.2