From 88a9f6c1da46859d90c60eed1756759a8acb0df5 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Wed, 24 Aug 2022 22:07:00 -0700
Subject: [PATCH] fix deprecated imports

---
 src/openpower/decoder/isa/caller.py                      | 2 +-
 src/openpower/decoder/isa/pypowersim.py                  | 2 +-
 src/openpower/decoder/isa/radixmmu.py                    | 2 +-
 src/openpower/decoder/isa/test_caller_fp.py              | 2 +-
 src/openpower/decoder/isa/test_caller_ldst_exceptions.py | 2 +-
 src/openpower/decoder/isa/test_caller_radix.py           | 2 +-
 src/openpower/decoder/isa/test_caller_setvl.py           | 2 +-
 src/openpower/decoder/isa/test_caller_svindex.py         | 2 +-
 src/openpower/decoder/isa/test_caller_svp64_bc.py        | 2 +-
 src/openpower/decoder/isa/test_caller_svp64_dct.py       | 2 +-
 src/openpower/decoder/isa/test_caller_svp64_fft.py       | 2 +-
 src/openpower/decoder/isa/test_caller_svp64_mapreduce.py | 2 +-
 src/openpower/decoder/isa/test_caller_svp64_matrix.py    | 2 +-
 src/openpower/decoder/isa/test_caller_svstate.py         | 2 +-
 src/openpower/decoder/isa/test_caller_transcendentals.py | 2 +-
 src/openpower/decoder/isa/test_runner.py                 | 2 +-
 src/openpower/decoder/orderedset.py                      | 5 +++--
 src/openpower/decoder/power_pseudo.py                    | 2 +-
 src/openpower/simulator/test_sim.py                      | 2 +-
 19 files changed, 21 insertions(+), 20 deletions(-)

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index a7d626fc..b5d9f5a5 100644
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -14,7 +14,7 @@ related bugs:
 """
 
 import re
-from nmigen.back.pysim import Settle
+from nmigen.sim import Settle
 from functools import wraps
 from copy import copy, deepcopy
 from openpower.decoder.orderedset import OrderedSet
diff --git a/src/openpower/decoder/isa/pypowersim.py b/src/openpower/decoder/isa/pypowersim.py
index cb7964fc..20edf565 100644
--- a/src/openpower/decoder/isa/pypowersim.py
+++ b/src/openpower/decoder/isa/pypowersim.py
@@ -1,5 +1,5 @@
 from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay, Settle
+from nmigen.sim import Simulator, Delay, Settle
 import sys
 import getopt
 import struct
diff --git a/src/openpower/decoder/isa/radixmmu.py b/src/openpower/decoder/isa/radixmmu.py
index 44786788..c22a484a 100644
--- a/src/openpower/decoder/isa/radixmmu.py
+++ b/src/openpower/decoder/isa/radixmmu.py
@@ -13,7 +13,7 @@ related bugs:
 * https://bugs.libre-soc.org/show_bug.cgi?id=604
 """
 
-#from nmigen.back.pysim import Settle
+#from nmigen.sim import Settle
 from copy import copy
 from openpower.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
                                         selectconcat)
diff --git a/src/openpower/decoder/isa/test_caller_fp.py b/src/openpower/decoder/isa/test_caller_fp.py
index b5f2bcec..1b11dfc6 100644
--- a/src/openpower/decoder/isa/test_caller_fp.py
+++ b/src/openpower/decoder/isa/test_caller_fp.py
@@ -1,5 +1,5 @@
 from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay, Settle
+from nmigen.sim import Simulator, Delay, Settle
 from nmutil.formaltest import FHDLTestCase
 import unittest
 from openpower.decoder.isa.caller import ISACaller
diff --git a/src/openpower/decoder/isa/test_caller_ldst_exceptions.py b/src/openpower/decoder/isa/test_caller_ldst_exceptions.py
index 58beb304..c9982365 100644
--- a/src/openpower/decoder/isa/test_caller_ldst_exceptions.py
+++ b/src/openpower/decoder/isa/test_caller_ldst_exceptions.py
@@ -1,5 +1,5 @@
 from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay, Settle
+from nmigen.sim import Simulator, Delay, Settle
 from nmutil.formaltest import FHDLTestCase
 import unittest
 from openpower.decoder.isa.caller import ISACaller
diff --git a/src/openpower/decoder/isa/test_caller_radix.py b/src/openpower/decoder/isa/test_caller_radix.py
index d5fe3ef1..29759b7b 100644
--- a/src/openpower/decoder/isa/test_caller_radix.py
+++ b/src/openpower/decoder/isa/test_caller_radix.py
@@ -1,5 +1,5 @@
 from nmigen import Module, Signal
-#from nmigen.back.pysim import Simulator, Delay, Settle
+#from nmigen.sim import Simulator, Delay, Settle
 from nmutil.formaltest import FHDLTestCase
 import unittest
 from openpower.decoder.isa.caller import ISACaller
diff --git a/src/openpower/decoder/isa/test_caller_setvl.py b/src/openpower/decoder/isa/test_caller_setvl.py
index e1f66505..be118bd8 100644
--- a/src/openpower/decoder/isa/test_caller_setvl.py
+++ b/src/openpower/decoder/isa/test_caller_setvl.py
@@ -1,5 +1,5 @@
 from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay, Settle
+from nmigen.sim import Simulator, Delay, Settle
 from nmutil.formaltest import FHDLTestCase
 import unittest
 from openpower.decoder.isa.caller import ISACaller
diff --git a/src/openpower/decoder/isa/test_caller_svindex.py b/src/openpower/decoder/isa/test_caller_svindex.py
index d91a07e6..ad4a1987 100644
--- a/src/openpower/decoder/isa/test_caller_svindex.py
+++ b/src/openpower/decoder/isa/test_caller_svindex.py
@@ -2,7 +2,7 @@
 svindex SVG,rmm,SVd,ew,yx,mm,sk
 """
 from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay, Settle
+from nmigen.sim import Simulator, Delay, Settle
 from nmutil.formaltest import FHDLTestCase
 import unittest
 from openpower.decoder.isa.caller import ISACaller
diff --git a/src/openpower/decoder/isa/test_caller_svp64_bc.py b/src/openpower/decoder/isa/test_caller_svp64_bc.py
index d42d7fbd..1b814a65 100644
--- a/src/openpower/decoder/isa/test_caller_svp64_bc.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_bc.py
@@ -1,5 +1,5 @@
 from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay, Settle
+from nmigen.sim import Simulator, Delay, Settle
 from nmutil.formaltest import FHDLTestCase
 import unittest
 from openpower.decoder.isa.caller import ISACaller
diff --git a/src/openpower/decoder/isa/test_caller_svp64_dct.py b/src/openpower/decoder/isa/test_caller_svp64_dct.py
index 9a8c1158..ce64cd2d 100644
--- a/src/openpower/decoder/isa/test_caller_svp64_dct.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_dct.py
@@ -1,5 +1,5 @@
 from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay, Settle
+from nmigen.sim import Simulator, Delay, Settle
 from nmutil.formaltest import FHDLTestCase
 from openpower.decoder.power_decoder import (create_pdecode)
 from openpower.simulator.program import Program
diff --git a/src/openpower/decoder/isa/test_caller_svp64_fft.py b/src/openpower/decoder/isa/test_caller_svp64_fft.py
index 81602fa3..114e8853 100644
--- a/src/openpower/decoder/isa/test_caller_svp64_fft.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_fft.py
@@ -1,5 +1,5 @@
 from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay, Settle
+from nmigen.sim import Simulator, Delay, Settle
 from nmutil.formaltest import FHDLTestCase
 import unittest
 from openpower.decoder.power_decoder import (create_pdecode)
diff --git a/src/openpower/decoder/isa/test_caller_svp64_mapreduce.py b/src/openpower/decoder/isa/test_caller_svp64_mapreduce.py
index 5fd6968a..6c6f751b 100644
--- a/src/openpower/decoder/isa/test_caller_svp64_mapreduce.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_mapreduce.py
@@ -1,5 +1,5 @@
 from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay, Settle
+from nmigen.sim import Simulator, Delay, Settle
 from nmutil.formaltest import FHDLTestCase
 import unittest
 from openpower.decoder.isa.caller import ISACaller
diff --git a/src/openpower/decoder/isa/test_caller_svp64_matrix.py b/src/openpower/decoder/isa/test_caller_svp64_matrix.py
index 43f14c8e..051199c8 100644
--- a/src/openpower/decoder/isa/test_caller_svp64_matrix.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_matrix.py
@@ -1,5 +1,5 @@
 from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay, Settle
+from nmigen.sim import Simulator, Delay, Settle
 from nmutil.formaltest import FHDLTestCase
 import unittest
 from openpower.decoder.isa.caller import ISACaller
diff --git a/src/openpower/decoder/isa/test_caller_svstate.py b/src/openpower/decoder/isa/test_caller_svstate.py
index 5ba0f77f..7612b5c6 100644
--- a/src/openpower/decoder/isa/test_caller_svstate.py
+++ b/src/openpower/decoder/isa/test_caller_svstate.py
@@ -1,7 +1,7 @@
 """SVP64 unit test for doing strange things to SVSTATE, manually.
 """
 from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay, Settle
+from nmigen.sim import Simulator, Delay, Settle
 from nmutil.formaltest import FHDLTestCase
 import unittest
 from openpower.decoder.isa.caller import ISACaller
diff --git a/src/openpower/decoder/isa/test_caller_transcendentals.py b/src/openpower/decoder/isa/test_caller_transcendentals.py
index f5536f06..08488bfb 100644
--- a/src/openpower/decoder/isa/test_caller_transcendentals.py
+++ b/src/openpower/decoder/isa/test_caller_transcendentals.py
@@ -1,5 +1,5 @@
 from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay, Settle
+from nmigen.sim import Simulator, Delay, Settle
 from nmutil.formaltest import FHDLTestCase
 import unittest
 from openpower.decoder.isa.caller import ISACaller
diff --git a/src/openpower/decoder/isa/test_runner.py b/src/openpower/decoder/isa/test_runner.py
index b49ec6ff..b84354cc 100644
--- a/src/openpower/decoder/isa/test_runner.py
+++ b/src/openpower/decoder/isa/test_runner.py
@@ -1,5 +1,5 @@
 from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Settle
+from nmigen.sim import Simulator, Settle
 from openpower.decoder.isa.caller import ISACaller
 from openpower.decoder.power_decoder import create_pdecode
 from openpower.decoder.power_decoder2 import (PowerDecode2)
diff --git a/src/openpower/decoder/orderedset.py b/src/openpower/decoder/orderedset.py
index d5f0b411..aa237f56 100644
--- a/src/openpower/decoder/orderedset.py
+++ b/src/openpower/decoder/orderedset.py
@@ -1,9 +1,10 @@
 # Originally from http://code.activestate.com/recipes/576694/
 # cut down to minimum
 
-import collections
+from collections.abc import MutableSet
 
-class OrderedSet(collections.MutableSet):
+
+class OrderedSet(MutableSet):
 
     def __init__(self, iterable=None):
         self.end = end = [] 
diff --git a/src/openpower/decoder/power_pseudo.py b/src/openpower/decoder/power_pseudo.py
index 05d5938a..f8d87dce 100644
--- a/src/openpower/decoder/power_pseudo.py
+++ b/src/openpower/decoder/power_pseudo.py
@@ -16,7 +16,7 @@ import astor
 import ast
 
 from openpower.decoder.power_decoder import create_pdecode
-from nmigen.back.pysim import Simulator, Delay
+from nmigen.sim import Simulator, Delay
 from nmigen import Module, Signal
 
 from openpower.decoder.pseudo.parser import GardenSnakeCompiler
diff --git a/src/openpower/simulator/test_sim.py b/src/openpower/simulator/test_sim.py
index 0b6f2230..7c240bd8 100644
--- a/src/openpower/simulator/test_sim.py
+++ b/src/openpower/simulator/test_sim.py
@@ -1,6 +1,6 @@
 import unittest
 from nmigen import Module
-from nmigen.back.pysim import Simulator, Delay, Settle
+from nmigen.sim import Simulator, Delay, Settle
 from nmutil.formaltest import FHDLTestCase
 from openpower.decoder.power_decoder import create_pdecode
 from openpower.decoder.power_decoder2 import (PowerDecode2)
-- 
2.30.2