From 88cad84baf99c032409c2de03f151c4ccf771fbf Mon Sep 17 00:00:00 2001 From: Kazu Hirata Date: Sat, 14 Sep 2002 13:12:56 +0000 Subject: [PATCH] haifa-sched.c: Follow spelling conventions. * haifa-sched.c: Follow spelling conventions. * regclass.c: Likewise. * regrename.c: Likewise. * config/fp-bit.c: Likewise. * config/frv/frv.h: Likewise. * config/m88k/m88k.c: Likewise. * config/mcore/mcore.c: Likewise. * config/rs6000/darwin.h: Likewise. * config/rs6000/gnu.h: Likewise. * config/rs6000/linux.h: Likewise. * config/rs6000/linux64.h: Likewise. * config/rs6000/rs6000.c: Likewise. * config/rs6000/rs6000.h: Likewise. * config/sh/sh.c: Likewise. * config/sparc/sparc.c: Likewise. * config/sparc/ultra1_2.md: Likewise. From-SVN: r57143 --- gcc/ChangeLog | 19 +++++++++++++++++++ gcc/config/fp-bit.c | 6 +++--- gcc/config/frv/frv.h | 4 ++-- gcc/config/m88k/m88k.c | 4 ++-- gcc/config/mcore/mcore.c | 6 +++--- gcc/config/rs6000/darwin.h | 2 +- gcc/config/rs6000/gnu.h | 2 +- gcc/config/rs6000/linux.h | 2 +- gcc/config/rs6000/linux64.h | 2 +- gcc/config/rs6000/rs6000.c | 2 +- gcc/config/rs6000/rs6000.h | 2 +- gcc/config/sh/sh.c | 2 +- gcc/config/sparc/sparc.c | 2 +- gcc/config/sparc/ultra1_2.md | 2 +- gcc/haifa-sched.c | 2 +- gcc/regclass.c | 4 ++-- gcc/regrename.c | 2 +- 17 files changed, 42 insertions(+), 23 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 26f089468bf..cbbacfb5368 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,22 @@ +2002-09-14 Kazu Hirata + + * haifa-sched.c: Follow spelling conventions. + * regclass.c: Likewise. + * regrename.c: Likewise. + * config/fp-bit.c: Likewise. + * config/frv/frv.h: Likewise. + * config/m88k/m88k.c: Likewise. + * config/mcore/mcore.c: Likewise. + * config/rs6000/darwin.h: Likewise. + * config/rs6000/gnu.h: Likewise. + * config/rs6000/linux.h: Likewise. + * config/rs6000/linux64.h: Likewise. + * config/rs6000/rs6000.c: Likewise. + * config/rs6000/rs6000.h: Likewise. + * config/sh/sh.c: Likewise. + * config/sparc/sparc.c: Likewise. + * config/sparc/ultra1_2.md: Likewise. + 2002-09-14 Stephane Carrez * config/m68hc11/m68hc11.md ("movdi_internal"): Allow any offsetable diff --git a/gcc/config/fp-bit.c b/gcc/config/fp-bit.c index 4253577acdf..6f27f5fa1c5 100644 --- a/gcc/config/fp-bit.c +++ b/gcc/config/fp-bit.c @@ -373,7 +373,7 @@ unpack_d (FLO_union_type * src, fp_number_type * dst) } else { - /* Zero exponent with non zero fraction - it's denormalized, + /* Zero exponent with nonzero fraction - it's denormalized, so there isn't a leading implicit one - we'll shift it so it gets one. */ dst->normal_exp = exp - EXPBIAS + 1; @@ -400,7 +400,7 @@ unpack_d (FLO_union_type * src, fp_number_type * dst) } else { - /* Non zero fraction, means nan */ + /* Nonzero fraction, means nan */ if (fraction & QUIET_NAN) { dst->class = CLASS_QNAN; @@ -940,7 +940,7 @@ __fpcmp_parts (fp_number_type * a, fp_number_type * b) -------+--------+-------- -inf(1)| a>b(1) | a==b(0) -------+--------+-------- - So since unordered must be non zero, just line up the columns... + So since unordered must be nonzero, just line up the columns... */ return b->sign - a->sign; } diff --git a/gcc/config/frv/frv.h b/gcc/config/frv/frv.h index a663c03b4d3..576b856e2aa 100644 --- a/gcc/config/frv/frv.h +++ b/gcc/config/frv/frv.h @@ -3542,12 +3542,12 @@ frv_ifcvt_modify_multiple_tests (CE_INFO, BB, &TRUE_EXPR, &FALSE_EXPR) #define PACKING_FLAG_USED_P() \ (optimize && flag_schedule_insns_after_reload && ISSUE_RATE > 1) -/* If the following macro is defined and non zero and deterministic +/* If the following macro is defined and nonzero and deterministic finite state automata are used for pipeline hazard recognition, the code making resource-constrained software pipelining is on. */ #define RCSP_SOFTWARE_PIPELINING 1 -/* If the following macro is defined and non zero and deterministic +/* If the following macro is defined and nonzero and deterministic finite state automata are used for pipeline hazard recognition, we will try to exchange insns in queue ready to improve the schedule. The more macro value, the more tries will be made. */ diff --git a/gcc/config/m88k/m88k.c b/gcc/config/m88k/m88k.c index 5da1a90b921..a9692e8cf33 100644 --- a/gcc/config/m88k/m88k.c +++ b/gcc/config/m88k/m88k.c @@ -246,7 +246,7 @@ output_load_const_dimode (operands) do the move. Otherwise, return 0 and the caller will emit the move normally. - SCRATCH if non zero can be used as a scratch register for the move + SCRATCH if nonzero can be used as a scratch register for the move operation. It is provided by a SECONDARY_RELOAD_* macro if needed. */ int @@ -315,7 +315,7 @@ emit_move_sequence (operands, mode, scratch) /* Return a legitimate reference for ORIG (either an address or a MEM) using the register REG. If PIC and the address is already position-independent, use ORIG. Newly generated position-independent - addresses go into a reg. This is REG if non zero, otherwise we + addresses go into a reg. This is REG if nonzero, otherwise we allocate register(s) as necessary. If this is called during reload, and we need a second temp register, then we use SCRATCH, which is provided via the SECONDARY_INPUT_RELOAD_CLASS mechanism. */ diff --git a/gcc/config/mcore/mcore.c b/gcc/config/mcore/mcore.c index 650d0dd8a96..be68d6606d9 100644 --- a/gcc/config/mcore/mcore.c +++ b/gcc/config/mcore/mcore.c @@ -1437,7 +1437,7 @@ mcore_output_movedouble (operands, mode) /* Predicates used by the templates. */ -/* Non zero if OP can be source of a simple move operation. */ +/* Nonzero if OP can be source of a simple move operation. */ int mcore_general_movsrc_operand (op, mode) @@ -1451,7 +1451,7 @@ mcore_general_movsrc_operand (op, mode) return general_operand (op, mode); } -/* Non zero if OP can be destination of a simple move operation. */ +/* Nonzero if OP can be destination of a simple move operation. */ int mcore_general_movdst_operand (op, mode) @@ -1483,7 +1483,7 @@ mcore_arith_reg_operand (op, mode) return 1; } -/* Non zero if OP should be recognized during reload for an ixh/ixw +/* Nonzero if OP should be recognized during reload for an ixh/ixw operand. See the ixh/ixw patterns. */ int diff --git a/gcc/config/rs6000/darwin.h b/gcc/config/rs6000/darwin.h index f3e1d715aa5..6bfc07ca981 100644 --- a/gcc/config/rs6000/darwin.h +++ b/gcc/config/rs6000/darwin.h @@ -214,7 +214,7 @@ Boston, MA 02111-1307, USA. */ : MAX ((COMPUTED), (SPECIFIED))) /* XXX: Darwin supports neither .quad, or .llong, but it also doesn't - support 64 bit powerpc either, so this just keeps things happy. */ + support 64 bit PowerPC either, so this just keeps things happy. */ #define DOUBLE_INT_ASM_OP "\t.quad\t" /* Get HOST_WIDE_INT and CONST_INT to be 32 bits, for compile time diff --git a/gcc/config/rs6000/gnu.h b/gcc/config/rs6000/gnu.h index 32bd906772c..9aeb696db2f 100644 --- a/gcc/config/rs6000/gnu.h +++ b/gcc/config/rs6000/gnu.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, - for powerpc machines running GNU. + for PowerPC machines running GNU. Copyright (C) 2001 Free Software Foundation, Inc. This file is part of GNU CC. diff --git a/gcc/config/rs6000/linux.h b/gcc/config/rs6000/linux.h index 0beaa618d94..95a4dd5791b 100644 --- a/gcc/config/rs6000/linux.h +++ b/gcc/config/rs6000/linux.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, - for powerpc machines running Linux. + for PowerPC machines running Linux. Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. Contributed by Michael Meissner (meissner@cygnus.com). diff --git a/gcc/config/rs6000/linux64.h b/gcc/config/rs6000/linux64.h index 8f96043706a..b617a6d0bd4 100644 --- a/gcc/config/rs6000/linux64.h +++ b/gcc/config/rs6000/linux64.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, - for 64 bit powerpc linux. + for 64 bit PowerPC linux. Copyright (C) 2000, 2001, 2002 Free Software Foundation, Inc. This file is part of GNU CC. diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index f7235401822..598e64c8029 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -8006,7 +8006,7 @@ print_operand_address (file, x) abort (); } -/* Target hook for assembling integer objects. The powerpc version has +/* Target hook for assembling integer objects. The PowerPC version has to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP is defined. It also needs to handle DI-mode objects on 64-bit targets. */ diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index f91afcde66a..930bbced084 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -160,7 +160,7 @@ extern int target_flags; /* Disable use of FPRs. */ #define MASK_SOFT_FLOAT 0x00000800 -/* Enable load/store multiple, even on powerpc */ +/* Enable load/store multiple, even on PowerPC */ #define MASK_MULTIPLE 0x00001000 #define MASK_MULTIPLE_SET 0x00002000 diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c index fa09f1da2b5..5921390a2bc 100644 --- a/gcc/config/sh/sh.c +++ b/gcc/config/sh/sh.c @@ -7137,7 +7137,7 @@ sh_pr_n_sets () return REG_N_SETS (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG); } -/* This Function returns non zero if the DFA based scheduler interface +/* This Function returns nonzero if the DFA based scheduler interface is to be used. At present this is supported for the SH4 only. */ static int sh_use_dfa_interface() diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c index 4a83b8a5612..37061be610d 100644 --- a/gcc/config/sparc/sparc.c +++ b/gcc/config/sparc/sparc.c @@ -3158,7 +3158,7 @@ pic_address_needs_scratch (x) /* Legitimize PIC addresses. If the address is already position-independent, we return ORIG. Newly generated position-independent addresses go into a - reg. This is REG if non zero, otherwise we allocate register(s) as + reg. This is REG if nonzero, otherwise we allocate register(s) as necessary. */ rtx diff --git a/gcc/config/sparc/ultra1_2.md b/gcc/config/sparc/ultra1_2.md index 84cbb4b622b..2194be7ad78 100644 --- a/gcc/config/sparc/ultra1_2.md +++ b/gcc/config/sparc/ultra1_2.md @@ -206,7 +206,7 @@ "us1_fpm + us1_fp_double + us1_slotany, nothing*3") ;; This is actually in theory dangerous, because it is possible -;; for the chip to prematurely dispatch the dependant instruction +;; for the chip to prematurely dispatch the dependent instruction ;; in the G stage, resulting in a 9 cycle stall. However I have never ;; been able to trigger this case myself even with hand written code, ;; so it must require some rare complicated pipeline state. diff --git a/gcc/haifa-sched.c b/gcc/haifa-sched.c index 68a7e0d508b..c5eb4d6ab9a 100644 --- a/gcc/haifa-sched.c +++ b/gcc/haifa-sched.c @@ -158,7 +158,7 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA static int issue_rate; -/* If the following variable value is non zero, the scheduler inserts +/* If the following variable value is nonzero, the scheduler inserts bubbles (nop insns). The value of variable affects on scheduler behavior only if automaton pipeline interface with multipass scheduling is used and hook dfa_bubble is defined. */ diff --git a/gcc/regclass.c b/gcc/regclass.c index 4718d9e90f8..672ee98fdff 100644 --- a/gcc/regclass.c +++ b/gcc/regclass.c @@ -2189,10 +2189,10 @@ static unsigned int reg_n_max; /* Allocate enough space to hold NUM_REGS registers for the tables used for reg_scan and flow_analysis that are indexed by the register number. If - NEW_P is non zero, initialize all of the registers, otherwise only + NEW_P is nonzero, initialize all of the registers, otherwise only initialize the new registers allocated. The same table is kept from function to function, only reallocating it when we need more room. If - RENUMBER_P is non zero, allocate the reg_renumber array also. */ + RENUMBER_P is nonzero, allocate the reg_renumber array also. */ void allocate_reg_info (num_regs, new_p, renumber_p) diff --git a/gcc/regrename.c b/gcc/regrename.c index 8300c37e34e..923652c422e 100644 --- a/gcc/regrename.c +++ b/gcc/regrename.c @@ -1243,7 +1243,7 @@ copy_value (dest, src, vd) return; /* Do not propagate copies to the stack pointer, as that can leave - memory accesses with no scheduling dependancy on the stack update. */ + memory accesses with no scheduling dependency on the stack update. */ if (dr == STACK_POINTER_REGNUM) return; -- 2.30.2