From 89210d00fea0429d0193efd9250c8ed2b07a9a53 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 9 Mar 2020 16:17:12 +0000 Subject: [PATCH] more comments for LDSTCompUnit --- src/soc/experiment/compldst.py | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/src/soc/experiment/compldst.py b/src/soc/experiment/compldst.py index 6a8cb358..f9458cdf 100644 --- a/src/soc/experiment/compldst.py +++ b/src/soc/experiment/compldst.py @@ -57,6 +57,7 @@ class LDSTCompUnit(Elaboratable): * :isalu_i: ADD/SUB is being "issued" (aka issue_alu_i) * :shadown_i: Inverted-shadow is being held (stops STORE *and* WRITE) * :go_rd_i: read is being actioned (latches in src regs) + * :go_wr_i: write mode (exactly like ALU CompUnit) * :go_ad_i: address is being actioned (triggers actual mem LD) * :go_st_i: store is being actioned (triggers actual mem STORE) * :go_die_i: resets the unit back to "wait for issue" @@ -69,9 +70,14 @@ class LDSTCompUnit(Elaboratable): * :adr_rel_o: request address (from mem) * :sto_rel_o: request store (to mem) * :req_rel_o: request write (result) - - Note: adr_rel, sto_rel, req_rel must all be acknowledged in a - single cycle. + * :load_mem_o: activate memory LOAD + * :stwd_mem_o: activate memory STORE + + Note: load_mem_o, stwd_mem_o and req_rel_o MUST all be acknowledged + in a single cycle and the CompUnit set back to doing another op. + This means deasserting go_st_i, go_ad_i or go_wr_i as appropriate + depending on whether the operation is a STORE, LD, or a straight + ALU operation respectively. Control Data (out) ------------------ -- 2.30.2