From 89290ef5e4ca1189006a7ceef49aeb1270ff8b8f Mon Sep 17 00:00:00 2001 From: lkcl Date: Tue, 15 Dec 2020 03:38:57 +0000 Subject: [PATCH] --- openpower/sv/svp_rewrite/svp64.mdwn | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn index c5d40949f..f837192e1 100644 --- a/openpower/sv/svp_rewrite/svp64.mdwn +++ b/openpower/sv/svp_rewrite/svp64.mdwn @@ -34,7 +34,9 @@ defined in the Prefix Fields section. One bit indicates the mode: CR or Int predication. The two types may not be mixed. -Twin predication uses the same encoding thus allowing either the same register (r3 or r10) to be used for both src and dest, or different regs (one for src, one for dest). +Integer Twin predication has a second set if 3 bits that uses the same encoding thus allowing either the same register (r3 or r10) to be used for both src and dest, or different regs (one for src, one for dest). + +Likewise CR based twin predication has a second set of 3 bits, allowing a different test to be applied. ### Integer Predication -- 2.30.2