From 893779cc020424b6555cb851fd2659597174461a Mon Sep 17 00:00:00 2001 From: Nick Clifton Date: Wed, 19 Aug 1998 10:56:21 -0600 Subject: [PATCH] thumb.md (extendqisi2_insn): Cope with REG + OFFSET addressing. * config/arm/thumb.md (extendqisi2_insn): Cope with REG + OFFSET addressing. From-SVN: r21862 --- gcc/config/arm/thumb.md | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/gcc/config/arm/thumb.md b/gcc/config/arm/thumb.md index 0369bb1c6b0..93d0c050314 100644 --- a/gcc/config/arm/thumb.md +++ b/gcc/config/arm/thumb.md @@ -484,7 +484,23 @@ { ops[1] = XEXP (XEXP (operands[1], 0), 0); ops[2] = XEXP (XEXP (operands[1], 0), 1); - output_asm_insn (\"ldrsb\\t%0, [%1, %2]\", ops); + + if (GET_CODE (ops[1]) == REG && GET_CODE (ops[2]) == REG) + output_asm_insn (\"ldrsb\\t%0, [%1, %2]\", ops); + else if (GET_CODE (ops[1]) == REG) + { + if (REGNO (ops[1]) == REGNO (operands[0])) + output_asm_insn (\"ldrb\\t%0, [%1, %2]\;lsl\\t%0, %0, #24\;asr\\t%0, %0, #24\", ops); + else + output_asm_insn (\"mov\\t%0, %2\;ldrsb\\t%0, [%1, %0]\", ops); + } + else + { + if (REGNO (ops[2]) == REGNO (operands[0])) + output_asm_insn (\"ldrb\\t%0, [%2, %1]\;lsl\\t%0, %0, #24\;asr\\t%0, %0, #24\", ops); + else + output_asm_insn (\"mov\\t%0, %2\;ldrsb\\t%0, [%1, %0]\", ops); + } } else if (REGNO (operands[0]) == REGNO (XEXP (operands[1], 0))) { -- 2.30.2