From 893accd585e3b7fd918bc166d107b1df4d79813c Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 25 Jul 2018 09:29:38 +0100 Subject: [PATCH] add fastslave axi defines --- src/bsv/bsv_lib/soc_template.bsv | 2 ++ src/bsv/peripheral_gen/base.py | 15 +++++++++++++++ src/bsv/peripheral_gen/rgbttl.py | 9 +++++++++ src/bsv/pinmux_generator.py | 3 ++- 4 files changed, 28 insertions(+), 1 deletion(-) diff --git a/src/bsv/bsv_lib/soc_template.bsv b/src/bsv/bsv_lib/soc_template.bsv index 414f14d..addc7ce 100644 --- a/src/bsv/bsv_lib/soc_template.bsv +++ b/src/bsv/bsv_lib/soc_template.bsv @@ -31,6 +31,8 @@ package Soc; import slow_peripherals::*; `include "defines.bsv" `include "instance_defines.bsv" + /*====== AXI4 Lite slave declarations =======*/ +{3} `ifdef DMA import DMA :: *; diff --git a/src/bsv/peripheral_gen/base.py b/src/bsv/peripheral_gen/base.py index 0ef4cd2..6c455fa 100644 --- a/src/bsv/peripheral_gen/base.py +++ b/src/bsv/peripheral_gen/base.py @@ -204,6 +204,21 @@ mkplic_rule = """\ """ +axi_fastslave_declarations = """\ +{0} +typedef TAdd#(LastGen_fastslave_num,1) Sdram_cfg_slave_num; +typedef TAdd#(Sdram_slave_num ,`ifdef SDRAM 1 `else 0 `endif ) Sdram_cfg_slave_num; +typedef TAdd#(Sdram_cfg_slave_num,`ifdef BOOTROM 1 `else 0 `endif ) BootRom_slave_num ; +typedef TAdd#(BootRom_slave_num ,`ifdef Debug 1 `else 0 `endif ) Debug_slave_num ; +typedef TAdd#(Debug_slave_num , `ifdef TCMemory 1 `else 0 `endif ) TCM_slave_num; +typedef TAdd#(TCM_slave_num ,`ifdef DMA 1 `else 0 `endif ) Dma_slave_num; +typedef TAdd#(Dma_slave_num ,1 ) SlowPeripheral_slave_num; +typedef TAdd#(SlowPeripheral_slave_num,`ifdef VME 1 `else 0 `endif ) VME_slave_num; +typedef TAdd#(VME_slave_num,`ifdef FlexBus 1 `else 0 `endif ) FlexBus_slave_num; +typedef TAdd#(FlexBus_slave_num,1) Num_Slaves; + +""" + axi_slave_declarations = """\ typedef 0 SlowMaster; {0} diff --git a/src/bsv/peripheral_gen/rgbttl.py b/src/bsv/peripheral_gen/rgbttl.py index 6f69d7b..1671d65 100644 --- a/src/bsv/peripheral_gen/rgbttl.py +++ b/src/bsv/peripheral_gen/rgbttl.py @@ -6,6 +6,15 @@ class rgbttl(PBase): def slowimport(self): return " import rgbttl_dummy :: *;" + def must_be_axi_master(self): + return True + + def axi_slave_name(self, name, ifacenum): + return '' + + def axi_slave_idx(self, idx, name, ifacenum, typ): + return ('', 0) + def num_axi_regs32(self): return 10 diff --git a/src/bsv/pinmux_generator.py b/src/bsv/pinmux_generator.py index 7def4f8..7844dfa 100644 --- a/src/bsv/pinmux_generator.py +++ b/src/bsv/pinmux_generator.py @@ -134,7 +134,7 @@ def write_soc(soc, soct, p, ifaces, iocells): imports = ifaces.slowimport() ifdecl = "" #ifaces.slowifdeclmux() + '\n' + ifaces.extifdecl() regdef = ifaces.axi_reg_def() - slavedecl = ifaces.axi_slave_idx() + slavedecl = ifaces.axi_fastslave_idx() fnaddrmap = ifaces.axi_addr_map() mkfast = ifaces.mkfast_peripheral() mkcon = ifaces.mk_connection() @@ -147,6 +147,7 @@ def write_soc(soc, soct, p, ifaces, iocells): ifacedef = ifaces.mk_ext_ifacedef() with open(soc, "w") as bsv_file: bsv_file.write(soct.format(imports, ifdecl, mkfast, + slavedecl, #'', '' #regdef, slavedecl, #'', mkslow, #fnaddrmap, mkslow, mkcon, mkcellcon, #pincon, inst, mkplic, -- 2.30.2