From 8943200ab8782988d5cea1bcb681c783ecf9163a Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 29 Mar 2023 17:32:41 +0100 Subject: [PATCH] put bit-field ordering for EXTRA2/3 into MSB0 order --- openpower/sv/rfc/ls010.mdwn | 32 +++++++++++++++++--------------- 1 file changed, 17 insertions(+), 15 deletions(-) diff --git a/openpower/sv/rfc/ls010.mdwn b/openpower/sv/rfc/ls010.mdwn index 73083fcec..c67f09f26 100644 --- a/openpower/sv/rfc/ls010.mdwn +++ b/openpower/sv/rfc/ls010.mdwn @@ -726,7 +726,8 @@ as there is insufficient bits to cover the full range. ## CR Field EXTRA3 CR Field encoding is essentially the same but made more complex due to CRs -being bit-based. See [[svp64/appendix]] for explanation and pseudocode. +being bit-based, because the application of SVP64 element-numbering applies +to the CR *Field* numbering not the CR register *bit* numbering. Note that Vectors may only start from `CR0, CR4, CR8, CR12, CR16, CR20`... and Scalars may only go from `CR0, CR1, ... CR31` @@ -736,14 +737,14 @@ For a 5-bit operand (BA, BB, BT): | Value | Mode | Range/Inc | 8..5 | 4..2 | 1..0 | |-------|------|---------------|-----------| --------|---------| -| 000 | Scalar | `CR0-CR7`/1 | 0b0000 | BA[4:2] | BA[1:0] | -| 001 | Scalar | `CR8-CR15`/1 | 0b0001 | BA[4:2] | BA[1:0] | -| 010 | Scalar | `CR16-CR23`/1 | 0b0010 | BA[4:2] | BA[1:0] | -| 011 | Scalar | `CR24-CR31`/1 | 0b0011 | BA[4:2] | BA[1:0] | -| 100 | Vector | `CR0-CR112`/16 | BA[4:2] 0 | 0b000 | BA[1:0] | -| 101 | Vector | `CR4-CR116`/16 | BA[4:2] 0 | 0b100 | BA[1:0] | -| 110 | Vector | `CR8-CR120`/16 | BA[4:2] 1 | 0b000 | BA[1:0] | -| 111 | Vector | `CR12-CR124`/16 | BA[4:2] 1 | 0b100 | BA[1:0] | +| 000 | Scalar | `CR0-CR7`/1 | 0b0000 | BA[0:2] | BA[3:4] | +| 001 | Scalar | `CR8-CR15`/1 | 0b0001 | BA[0:2] | BA[3:4] | +| 010 | Scalar | `CR16-CR23`/1 | 0b0010 | BA[0:2] | BA[3:4] | +| 011 | Scalar | `CR24-CR31`/1 | 0b0011 | BA[0:2] | BA[3:4] | +| 100 | Vector | `CR0-CR112`/16 | BA[0:2] 0 | 0b000 | BA[3:4] | +| 101 | Vector | `CR4-CR116`/16 | BA[0:2] 0 | 0b100 | BA[3:4] | +| 110 | Vector | `CR8-CR120`/16 | BA[0:2] 1 | 0b000 | BA[3:4] | +| 111 | Vector | `CR12-CR124`/16 | BA[0:2] 1 | 0b100 | BA[3:4] | For a 3-bit operand (e.g. BFA): @@ -761,20 +762,21 @@ For a 3-bit operand (e.g. BFA): ## CR EXTRA2 CR encoding is essentially the same but made more complex due to CRs -being bit-based. See separate section for explanation and pseudocode. +being bit-based, because the application of SVP64 element-numbering applies +to the CR *Field* numbering not the CR register *bit* numbering. +See separate section for explanation and pseudocode. Note that Vectors may only start from CR0, CR8, CR16, CR24, CR32... - Encoding shown MSB down to LSB For a 5-bit operand (BA, BB, BC): | Value | Mode | Range/Inc | 8..5 | 4..2 | 1..0 | |-------|--------|----------------|---------|---------|---------| -| 00 | Scalar | `CR0-CR7`/1 | 0b0000 | BA[4:2] | BA[1:0] | -| 01 | Scalar | `CR8-CR15`/1 | 0b0001 | BA[4:2] | BA[1:0] | -| 10 | Vector | `CR0-CR112`/16 | BA[4:2] 0 | 0b000 | BA[1:0] | -| 11 | Vector | `CR8-CR120`/16 | BA[4:2] 1 | 0b000 | BA[1:0] | +| 00 | Scalar | `CR0-CR7`/1 | 0b0000 | BA[0:2] | BA[3:4] | +| 01 | Scalar | `CR8-CR15`/1 | 0b0001 | BA[0:2] | BA[3:4] | +| 10 | Vector | `CR0-CR112`/16 | BA[0:2] 0 | 0b000 | BA[3:4] | +| 11 | Vector | `CR8-CR120`/16 | BA[0:2] 1 | 0b000 | BA[3:4] | For a 3-bit operand (e.g. BFA): -- 2.30.2