From 895204b6c8660a262c2cd802693a24e279b30d26 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 6 Nov 2018 17:51:11 +0000 Subject: [PATCH] elwidth rv_rem --- riscv/sv_insn_redirect.cc | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc index d91c751..7aa0b61 100644 --- a/riscv/sv_insn_redirect.cc +++ b/riscv/sv_insn_redirect.cc @@ -556,12 +556,32 @@ sv_reg_t sv_proc_t::rv_div(sv_reg_t const & lhs, sv_reg_t const & rhs) sv_sreg_t sv_proc_t::rv_rem(sv_sreg_t const & lhs, sv_sreg_t const & rhs) { - return lhs % rhs; + uint8_t bitwidth = _insn->src_bitwidth; + int64_t vlhs = 0; + int64_t vrhs = 0; + if (rv_int_op_prepare(lhs, rhs, vlhs, vrhs, bitwidth)) { + sv_sreg_t result = lhs % rhs; + fprintf(stderr, "rem result %lx %lx %lx\n", + (uint64_t)lhs, (uint64_t)rhs, (int64_t)result); + return result; + } + int64_t result = vlhs % vrhs; + return rv_int_op_finish(lhs, rhs, result, bitwidth); } sv_reg_t sv_proc_t::rv_rem(sv_reg_t const & lhs, sv_reg_t const & rhs) { - return lhs % rhs; + uint8_t bitwidth = _insn->src_bitwidth; + uint64_t vlhs = 0; + uint64_t vrhs = 0; + if (rv_int_op_prepare(lhs, rhs, vlhs, vrhs, bitwidth)) { + sv_reg_t result = lhs % rhs; + fprintf(stderr, "rem result %lx %lx %lx\n", + (uint64_t)lhs, (uint64_t)rhs, (uint64_t)result); + return result; + } + uint64_t result = vlhs % vrhs; + return rv_int_op_finish(lhs, rhs, result, bitwidth); } sv_reg_t sv_proc_t::rv_mul(sv_reg_t const & lhs, sv_reg_t const & rhs) -- 2.30.2