From 897ff7f2b363f566dcd0d3b846eec50e0e1dabed Mon Sep 17 00:00:00 2001 From: Shriya Sharma Date: Fri, 17 Nov 2023 15:32:18 +0000 Subject: [PATCH] Added English language description for lhaupsx instruction --- openpower/isa/pifixedloadshift.mdwn | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-) diff --git a/openpower/isa/pifixedloadshift.mdwn b/openpower/isa/pifixedloadshift.mdwn index d2a4445d..265ce4ec 100644 --- a/openpower/isa/pifixedloadshift.mdwn +++ b/openpower/isa/pifixedloadshift.mdwn @@ -13,7 +13,7 @@ # Load Byte and Zero with Post-Update Indexed -Z23-Form +X-Form * lbzupsx RT,RA,RB,SH @@ -41,7 +41,7 @@ Special Registers Altered: # Load Halfword and Zero with Post-Update Indexed -Z23-Form +X-Form * lhzupsx RT,RA,RB,SH @@ -53,7 +53,9 @@ Pseudo-code: Description: - Let the effective address (EA) be register RA. + Let the effective address (EA) be the contents of + register RA shifted by (SH+1). + The halfword in storage addressed by EA is loaded into RT[48:63]. RT[0:47] are set to 0. @@ -67,19 +69,20 @@ Special Registers Altered: # Load Halfword Algebraic with Post-Update Indexed -Z23-Form +X-Form -* lhaupsx RT,RA,RB +* lhaupsx RT,RA,RB,SH Pseudo-code: - EA <- (RA) + EA <- (RA)<<(SH+1) RT <- EXTS(MEM(EA, 2)) RA <- (RA) + (RB) Description: - Let the effective address (EA) be the register RA. + Let the effective address (EA) be the contents of + register RA shifted by (SH+1). The halfword in storage addressed by EA is loaded into RT[48:63]. RT[0:47] are filled with a copy of bit 0 of the loaded halfword. @@ -94,7 +97,7 @@ Special Registers Altered: # Load Word and Zero with Post-Update Indexed -Z23-Form +X-Form * lwzupsx RT,RA,RB @@ -121,7 +124,7 @@ Special Registers Altered: # Load Word Algebraic with Post-Update Indexed -Z23-Form +X-Form * lwaupsx RT,RA,RB @@ -148,7 +151,7 @@ Special Registers Altered: # Load Doubleword with Post-Update Indexed -Z23-Form +X-Form * ldupsx RT,RA,RB -- 2.30.2