From 8981b11f6c850fa98115e554b298cecba9bf048b Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 27 Oct 2018 08:40:15 +0100 Subject: [PATCH] replace sv_float64_t typedef with class derived from sv_regbase_t --- riscv/decode.h | 2 +- riscv/insns/fmax_d.h | 6 +++--- riscv/insns/fmin_d.h | 6 +++--- riscv/insns/fmsub_d.h | 2 +- riscv/insns/fnmadd_d.h | 3 ++- riscv/insns/fnmsub_d.h | 2 +- riscv/sv_insn_redirect.cc | 3 ++- riscv/sv_insn_redirect.h | 2 +- riscv/sv_reg.h | 16 ++++++++++++++++ 9 files changed, 30 insertions(+), 12 deletions(-) diff --git a/riscv/decode.h b/riscv/decode.h index 53e8378..e94f73e 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -252,7 +252,7 @@ inline freg_t freg(float128_t f) { return f; } #define fsgnj32(a, b, n, x) \ f32((((float32_t)f32(a)).v & ~F32_SIGN) | ((((x) ? ((float32_t)f32(a)).v : (n) ? F32_SIGN : 0) ^ ((float32_t)f32(b)).v) & F32_SIGN)) #define fsgnj64(a, b, n, x) \ - f64((f64(a).v & ~F64_SIGN) | ((((x) ? f64(a).v : (n) ? F64_SIGN : 0) ^ f64(b).v) & F64_SIGN)) + f64((((float64_t)f64(a)).v & ~F64_SIGN) | ((((x) ? ((float64_t)f64(a)).v : (n) ? F64_SIGN : 0) ^ ((float64_t)f64(b)).v) & F64_SIGN)) #define isNaNF128(x) isNaNF128UI(x.v[1], x.v[0]) inline float128_t defaultNaNF128() diff --git a/riscv/insns/fmax_d.h b/riscv/insns/fmax_d.h index 11491f5..6884ce1 100644 --- a/riscv/insns/fmax_d.h +++ b/riscv/insns/fmax_d.h @@ -1,9 +1,9 @@ require_extension('D'); require_fp; bool greater = f64_lt_quiet(f64(FRS2), f64(FRS1)) || - (f64_eq(f64(FRS2), f64(FRS1)) && (f64(FRS2).v & F64_SIGN)); -if (isNaNF64UI(f64(FRS1).v) && isNaNF64UI(f64(FRS2).v)) + (f64_eq(f64(FRS2), f64(FRS1)) && (((float64_t)f64(FRS2)).v & F64_SIGN)); +if (isNaNF64UI(((float64_t)f64(FRS1)).v) && isNaNF64UI(((float64_t)f64(FRS2)).v)) WRITE_FRD(f64(defaultNaNF64UI)); else - WRITE_FRD(greater || isNaNF64UI(f64(FRS2).v) ? FRS1 : FRS2); + WRITE_FRD(greater || isNaNF64UI(((float64_t)f64(FRS2)).v) ? FRS1 : FRS2); set_fp_exceptions; diff --git a/riscv/insns/fmin_d.h b/riscv/insns/fmin_d.h index 5cf349d..e179d33 100644 --- a/riscv/insns/fmin_d.h +++ b/riscv/insns/fmin_d.h @@ -1,9 +1,9 @@ require_extension('D'); require_fp; bool less = f64_lt_quiet(f64(FRS1), f64(FRS2)) || - (f64_eq(f64(FRS1), f64(FRS2)) && (f64(FRS1).v & F64_SIGN)); -if (isNaNF64UI(f64(FRS1).v) && isNaNF64UI(f64(FRS2).v)) + (f64_eq(f64(FRS1), f64(FRS2)) && (((float64_t)f64(FRS1)).v & F64_SIGN)); +if (isNaNF64UI(((float64_t)f64(FRS1)).v) && isNaNF64UI(((float64_t)f64(FRS2)).v)) WRITE_FRD(f64(defaultNaNF64UI)); else - WRITE_FRD(less || isNaNF64UI(f64(FRS2).v) ? FRS1 : FRS2); + WRITE_FRD(less || isNaNF64UI(((float64_t)f64(FRS2)).v) ? FRS1 : FRS2); set_fp_exceptions; diff --git a/riscv/insns/fmsub_d.h b/riscv/insns/fmsub_d.h index 5b5bc0f..5606213 100644 --- a/riscv/insns/fmsub_d.h +++ b/riscv/insns/fmsub_d.h @@ -1,5 +1,5 @@ require_extension('D'); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(f64_mulAdd(f64(FRS1), f64(FRS2), f64(f64(FRS3).v ^ F64_SIGN))); +WRITE_FRD(f64_mulAdd(f64(FRS1), f64(FRS2), f64(((float64_t)f64(FRS3)).v ^ F64_SIGN))); set_fp_exceptions; diff --git a/riscv/insns/fnmadd_d.h b/riscv/insns/fnmadd_d.h index e8dd743..ed31a6b 100644 --- a/riscv/insns/fnmadd_d.h +++ b/riscv/insns/fnmadd_d.h @@ -1,5 +1,6 @@ require_extension('D'); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(f64_mulAdd(f64(f64(FRS1).v ^ F64_SIGN), f64(FRS2), f64(f64(FRS3).v ^ F64_SIGN))); +WRITE_FRD(f64_mulAdd(f64(((float64_t)f64(FRS1)).v ^ F64_SIGN), f64(FRS2), f64(((float64_t)f64(FRS3)).v ^ F64_SIGN))); + set_fp_exceptions; diff --git a/riscv/insns/fnmsub_d.h b/riscv/insns/fnmsub_d.h index c29a0b9..c2062e5 100644 --- a/riscv/insns/fnmsub_d.h +++ b/riscv/insns/fnmsub_d.h @@ -1,5 +1,5 @@ require_extension('D'); require_fp; softfloat_roundingMode = RM; -WRITE_FRD(f64_mulAdd(f64(f64(FRS1).v ^ F64_SIGN), f64(FRS2), f64(FRS3))); +WRITE_FRD(f64_mulAdd(f64(((float64_t)f64(FRS1)).v ^ F64_SIGN), f64(FRS2), f64(FRS3))); set_fp_exceptions; diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc index 893a488..2be2e17 100644 --- a/riscv/sv_insn_redirect.cc +++ b/riscv/sv_insn_redirect.cc @@ -12,7 +12,8 @@ void (sv_proc_t::WRITE_FRD)(sv_float32_t value) void (sv_proc_t::WRITE_FRD)(sv_float64_t value) { - fprintf(stderr, "WRITE_FRD sv_float64_t %g\n", (double)value.v); + fprintf(stderr, "WRITE_FRD sv_float64_t %g\n", + (double)((float64_t)value).v); DO_WRITE_FREG( _insn->rd(), freg(value) ); } diff --git a/riscv/sv_insn_redirect.h b/riscv/sv_insn_redirect.h index 159a10b..a5a1c9e 100644 --- a/riscv/sv_insn_redirect.h +++ b/riscv/sv_insn_redirect.h @@ -57,7 +57,7 @@ class insn_t; //typedef reg_t sv_reg_t; //typedef sreg_t sv_sreg_t; //typedef float32_t sv_float32_t; -typedef float64_t sv_float64_t; +//typedef float64_t sv_float64_t; typedef float128_t sv_float128_t; //typedef freg_t sv_freg_t; diff --git a/riscv/sv_reg.h b/riscv/sv_reg.h index 70e1533..1c9eade 100644 --- a/riscv/sv_reg.h +++ b/riscv/sv_reg.h @@ -107,4 +107,20 @@ public: operator float32_t() const& { return reg; } }; +class sv_float64_t : public sv_regbase_t { +public: + sv_float64_t(float64_t _reg) : sv_regbase_t(), reg(_reg) { } // default elwidth + sv_float64_t(float64_t _reg, uint8_t _elwidth) : + sv_regbase_t(_elwidth), reg(_reg) + {} + sv_float64_t(float64_t _reg, int xlen, uint8_t _elwidth) : + sv_regbase_t(xlen, _elwidth), reg(_reg) + {} + + float64_t reg; +public: + + operator float64_t() const& { return reg; } +}; + #endif -- 2.30.2