From 89b3616d7e3318637c1550605703f140ecf7b65f Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Sun, 25 Jan 2015 07:22:56 -0500 Subject: [PATCH] arm: always set the IsFirstMicroop flag While the IsFirstMicroop flag exists it was only occasionally used in the ARM instructions that gem5 microOps and therefore couldn't be relied on to be correct. --- src/arch/arm/insts/macromem.cc | 11 +++++++++++ src/arch/arm/isa/templates/mem.isa | 17 ++++++++++++++++- src/arch/arm/isa/templates/mem64.isa | 5 ++++- src/cpu/static_inst.hh | 1 + 4 files changed, 32 insertions(+), 2 deletions(-) diff --git a/src/arch/arm/insts/macromem.cc b/src/arch/arm/insts/macromem.cc index 3158026db..5578354d9 100644 --- a/src/arch/arm/insts/macromem.cc +++ b/src/arch/arm/insts/macromem.cc @@ -220,6 +220,7 @@ MacroMemOp::MacroMemOp(const char *mnem, ExtMachInst machInst, --uop; (*uop)->setLastMicroop(); + microOps[0]->setFirstMicroop(); /* Take the control flags from the last microop for the macroop */ if ((*uop)->isControl()) @@ -335,6 +336,7 @@ PairMemOp::PairMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, assert(uop == µOps[numMicroops]); (*--uop)->setLastMicroop(); + microOps[0]->setFirstMicroop(); for (StaticInstPtr *curUop = microOps; !(*curUop)->isLastMicroop(); curUop++) { @@ -360,6 +362,7 @@ BigFpMemImmOp::BigFpMemImmOp(const char *mnem, ExtMachInst machInst, *++uop = new MicroStrQTFpXImmUop(machInst, dest, base, imm); } (*uop)->setLastMicroop(); + microOps[0]->setFirstMicroop(); } BigFpMemPostOp::BigFpMemPostOp(const char *mnem, ExtMachInst machInst, @@ -380,6 +383,7 @@ BigFpMemPostOp::BigFpMemPostOp(const char *mnem, ExtMachInst machInst, } *uop = new MicroAddXiUop(machInst, base, base, imm); (*uop)->setLastMicroop(); + microOps[0]->setFirstMicroop(); for (StaticInstPtr *curUop = microOps; !(*curUop)->isLastMicroop(); curUop++) { @@ -405,6 +409,7 @@ BigFpMemPreOp::BigFpMemPreOp(const char *mnem, ExtMachInst machInst, } *uop = new MicroAddXiUop(machInst, base, base, imm); (*uop)->setLastMicroop(); + microOps[0]->setFirstMicroop(); for (StaticInstPtr *curUop = microOps; !(*curUop)->isLastMicroop(); curUop++) { @@ -435,6 +440,7 @@ BigFpMemRegOp::BigFpMemRegOp(const char *mnem, ExtMachInst machInst, } (*uop)->setLastMicroop(); + microOps[0]->setFirstMicroop(); } BigFpMemLitOp::BigFpMemLitOp(const char *mnem, ExtMachInst machInst, @@ -447,6 +453,7 @@ BigFpMemLitOp::BigFpMemLitOp(const char *mnem, ExtMachInst machInst, microOps[0] = new MicroLdFp16LitUop(machInst, dest, imm); microOps[0]->setLastMicroop(); + microOps[0]->setFirstMicroop(); } VldMultOp::VldMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, @@ -540,6 +547,7 @@ VldMultOp::VldMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, assert(uopPtr); uopPtr->setDelayedCommit(); } + microOps[0]->setFirstMicroop(); microOps[numMicroops - 1]->setLastMicroop(); } @@ -807,6 +815,7 @@ VldSingleOp::VldSingleOp(const char *mnem, ExtMachInst machInst, assert(uopPtr); uopPtr->setDelayedCommit(); } + microOps[0]->setFirstMicroop(); microOps[numMicroops - 1]->setLastMicroop(); } @@ -901,6 +910,7 @@ VstMultOp::VstMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, assert(uopPtr); uopPtr->setDelayedCommit(); } + microOps[0]->setFirstMicroop(); microOps[numMicroops - 1]->setLastMicroop(); } @@ -1103,6 +1113,7 @@ VstSingleOp::VstSingleOp(const char *mnem, ExtMachInst machInst, assert(uopPtr); uopPtr->setDelayedCommit(); } + microOps[0]->setFirstMicroop(); microOps[numMicroops - 1]->setLastMicroop(); } diff --git a/src/arch/arm/isa/templates/mem.isa b/src/arch/arm/isa/templates/mem.isa index f1d1523f4..bac1cd211 100644 --- a/src/arch/arm/isa/templates/mem.isa +++ b/src/arch/arm/isa/templates/mem.isa @@ -1,6 +1,6 @@ // -*- mode:c++ -*- -// Copyright (c) 2010, 2012 ARM Limited +// Copyright (c) 2010, 2012, 2014 ARM Limited // All rights reserved // // The license below extends only to copyright in the software and shall @@ -883,6 +883,7 @@ def template RfeConstructor {{ #if %(use_pc)d uops[++uopIdx] = new %(pc_decl)s; #endif + uops[0]->setFirstMicroop(); uops[uopIdx]->setLastMicroop(); #endif } @@ -905,6 +906,7 @@ def template SrsConstructor {{ uops = new StaticInstPtr[numMicroops]; uops[0] = new %(acc_name)s(machInst, _regMode, _mode, _wb); uops[0]->setDelayedCommit(); + uops[0]->setFirstMicroop(); uops[1] = new %(wb_decl)s; uops[1]->setLastMicroop(); #endif @@ -944,6 +946,7 @@ def template LoadStoreDImmConstructor {{ assert(numMicroops >= 2); uops = new StaticInstPtr[numMicroops]; uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, _imm); + uops[0]->setFirstMicroop(); uops[0]->setDelayedCommit(); uops[1] = new %(wb_decl)s; uops[1]->setLastMicroop(); @@ -972,6 +975,7 @@ def template StoreExDImmConstructor {{ uops[0] = new %(acc_name)s(machInst, _result, _dest, _dest2, _base, _add, _imm); uops[0]->setDelayedCommit(); + uops[0]->setFirstMicroop(); uops[1] = new %(wb_decl)s; uops[1]->setLastMicroop(); #endif @@ -995,6 +999,7 @@ def template LoadStoreImmConstructor {{ uops = new StaticInstPtr[numMicroops]; uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _imm); uops[0]->setDelayedCommit(); + uops[0]->setFirstMicroop(); uops[1] = new %(wb_decl)s; uops[1]->setLastMicroop(); #endif @@ -1021,6 +1026,7 @@ def template StoreExImmConstructor {{ uops[0] = new %(acc_name)s(machInst, _result, _dest, _base, _add, _imm); uops[0]->setDelayedCommit(); + uops[0]->setFirstMicroop(); uops[1] = new %(wb_decl)s; uops[1]->setLastMicroop(); #endif @@ -1049,6 +1055,7 @@ def template StoreDRegConstructor {{ uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, _shiftAmt, _shiftType, _index); uops[0]->setDelayedCommit(); + uops[0]->setFirstMicroop(); uops[1] = new %(wb_decl)s; uops[1]->setLastMicroop(); #endif @@ -1076,6 +1083,7 @@ def template StoreRegConstructor {{ uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _shiftAmt, _shiftType, _index); uops[0]->setDelayedCommit(); + uops[0]->setFirstMicroop(); uops[1] = new %(wb_decl)s; uops[1]->setLastMicroop(); #endif @@ -1105,6 +1113,7 @@ def template LoadDRegConstructor {{ IntRegIndex wbIndexReg = INTREG_UREG0; uops[0] = new MicroUopRegMov(machInst, INTREG_UREG0, _index); uops[0]->setDelayedCommit(); + uops[0]->setFirstMicroop(); uops[1] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, _shiftAmt, _shiftType, _index); uops[1]->setDelayedCommit(); @@ -1115,6 +1124,7 @@ def template LoadDRegConstructor {{ uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, _shiftAmt, _shiftType, _index); uops[0]->setDelayedCommit(); + uops[0]->setFirstMicroop(); uops[1] = new %(wb_decl)s; uops[1]->setLastMicroop(); } @@ -1147,6 +1157,7 @@ def template LoadRegConstructor {{ uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add, _shiftAmt, _shiftType, _index); uops[0]->setDelayedCommit(); + uops[0]->setFirstMicroop(); uops[1] = new %(wb_decl)s; uops[1]->setDelayedCommit(); uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0); @@ -1161,6 +1172,7 @@ def template LoadRegConstructor {{ IntRegIndex wbIndexReg = INTREG_UREG0; uops[0] = new MicroUopRegMov(machInst, INTREG_UREG0, _index); uops[0]->setDelayedCommit(); + uops[0]->setFirstMicroop(); uops[1] = new %(acc_name)s(machInst, _dest, _base, _add, _shiftAmt, _shiftType, _index); uops[1]->setDelayedCommit(); @@ -1171,6 +1183,7 @@ def template LoadRegConstructor {{ uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _shiftAmt, _shiftType, _index); uops[0]->setDelayedCommit(); + uops[0]->setFirstMicroop(); uops[1] = new %(wb_decl)s; uops[1]->setLastMicroop(); @@ -1209,6 +1222,7 @@ def template LoadImmConstructor {{ uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add, _imm); uops[0]->setDelayedCommit(); + uops[0]->setFirstMicroop(); uops[1] = new %(wb_decl)s; uops[1]->setDelayedCommit(); uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0); @@ -1233,6 +1247,7 @@ def template LoadImmConstructor {{ } else { uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _imm); uops[0]->setDelayedCommit(); + uops[0]->setFirstMicroop(); uops[1] = new %(wb_decl)s; uops[1]->setLastMicroop(); } diff --git a/src/arch/arm/isa/templates/mem64.isa b/src/arch/arm/isa/templates/mem64.isa index 3d6cadb5d..72ee882a7 100644 --- a/src/arch/arm/isa/templates/mem64.isa +++ b/src/arch/arm/isa/templates/mem64.isa @@ -1,6 +1,6 @@ // -*- mode:c++ -*- -// Copyright (c) 2011-2013 ARM Limited +// Copyright (c) 2011-2014 ARM Limited // All rights reserved // // The license below extends only to copyright in the software and shall @@ -556,6 +556,7 @@ def template LoadStoreImm64Constructor {{ uops = new StaticInstPtr[numMicroops]; uops[0] = new %(acc_name)s(machInst, _dest, _base, _imm); uops[0]->setDelayedCommit(); + uops[0]->setFirstMicroop(); uops[1] = new %(wb_decl)s; uops[1]->setLastMicroop(); #endif @@ -615,6 +616,7 @@ def template LoadStoreReg64Constructor {{ uops[0] = new %(acc_name)s(machInst, _dest, _base, _offset, _type, _shiftAmt); uops[0]->setDelayedCommit(); + uops[0]->setFirstMicroop(); uops[1] = new %(wb_decl)s; uops[1]->setLastMicroop(); #endif @@ -666,6 +668,7 @@ def template LoadStoreLit64Constructor {{ uops = new StaticInstPtr[numMicroops]; uops[0] = new %(acc_name)s(machInst, _dest, _imm); uops[0]->setDelayedCommit(); + uops[0]->setFirstMicroop(); uops[1] = new %(wb_decl)s; uops[1]->setLastMicroop(); #endif diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh index 42e215388..7206a2616 100644 --- a/src/cpu/static_inst.hh +++ b/src/cpu/static_inst.hh @@ -171,6 +171,7 @@ class StaticInst : public RefCounted, public StaticInstFlags bool isMicroBranch() const { return flags[IsMicroBranch]; } //@} + void setFirstMicroop() { flags[IsFirstMicroop] = true; } void setLastMicroop() { flags[IsLastMicroop] = true; } void setDelayedCommit() { flags[IsDelayedCommit] = true; } void setFlag(Flags f) { flags[f] = true; } -- 2.30.2