From 89fe1755c123b58af69ae92ea661dba1f0354141 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 4 Sep 2022 18:06:55 +0100 Subject: [PATCH] --- openpower/sv.mdwn | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn index da62de4da..25120e3ab 100644 --- a/openpower/sv.mdwn +++ b/openpower/sv.mdwn @@ -101,6 +101,7 @@ Comparative Basic Design Principle: guaranteeing binary interoperability) * Intel AVX-512 (and below): Hybrid Packed-Predicated SIMD with no instruction-overloading, guaranteeing binary interoperability + but penalising the ISA with uncontrolled opcode proliferation. * ARM SVE/SVE2: Hybrid Packed-Predicated SIMD with instruction-overloading that destroys binary interoperability. This is hidden behind the misuse of the word "Scalable". @@ -108,11 +109,11 @@ Comparative Basic Design Principle: that destroys binary interoperability. * SVP64: Cray-style Scalable Vector with no instruction-overloaded meanings. The regfile numbers and bitwidths shall **not** change - in a future revision: "Silicon Partner" Scaling is prohibited, + in a future revision (for the same instruction encoding): + "Silicon Partner" Scaling is prohibited, in order to guarantee binary interoperability. Future revisions - of SVP64 may extend VSX to achieve larger regfiles and once - chosen, change that results in instruction-overloaded - non-interoperability will also be prohibited. + of SVP64 may extend VSX instructions to achieve larger regfiles, and + non-interoperability on the same will likewise be prohibited. SV comprises several [[sv/compliancy_levels]] suited to Embedded, Energy efficient High-Performance Compute, Distributed Computing and Advanced -- 2.30.2