From 89ff5b1e514e5473a3fa2700517904caf0bfdfa2 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Timur=20Krist=C3=B3f?= Date: Sat, 7 Mar 2020 18:26:52 +0100 Subject: [PATCH] aco: Implement load_view_index for TCS and TES. MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Signed-off-by: Timur Kristóf Reviewed-by: Rhys Perry Part-of: --- src/amd/compiler/aco_instruction_selection.cpp | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index 0e8624cf51c..a1c3568bcde 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -6172,14 +6172,16 @@ void visit_intrinsic(isel_context *ctx, nir_intrinsic_instr *instr) Operand(0u), get_arg(ctx, ctx->args->ac.front_face)).def(0).setHint(vcc); break; } - case nir_intrinsic_load_view_index: - case nir_intrinsic_load_layer_id: { - if (instr->intrinsic == nir_intrinsic_load_view_index && (ctx->stage & (sw_vs | sw_gs))) { + case nir_intrinsic_load_view_index: { + if (ctx->stage & (sw_vs | sw_gs | sw_tcs | sw_tes)) { Temp dst = get_ssa_temp(ctx, &instr->dest.ssa); bld.copy(Definition(dst), Operand(get_arg(ctx, ctx->args->ac.view_index))); break; } + /* fallthrough */ + } + case nir_intrinsic_load_layer_id: { unsigned idx = nir_intrinsic_base(instr); bld.vintrp(aco_opcode::v_interp_mov_f32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), Operand(2u), bld.m0(get_arg(ctx, ctx->args->ac.prim_mask)), idx, 0); -- 2.30.2