From 8a11699c4ed3783607bf1558fa94dbb3abe5190c Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 20 Oct 2022 22:46:32 +0100 Subject: [PATCH] --- openpower/sv/rfc/ls003.mdwn | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/openpower/sv/rfc/ls003.mdwn b/openpower/sv/rfc/ls003.mdwn index 78154cd2d..a43cfe676 100644 --- a/openpower/sv/rfc/ls003.mdwn +++ b/openpower/sv/rfc/ls003.mdwn @@ -61,15 +61,20 @@ **Motivation** Similar to `maddhdu` and `maddld`, but allow for a big-integer rolling -accumulation affect. As the second result location is implicitly defined as the register after the first result (RS=RT+1), the Scalar Register set can be used -for vector computation. -Similar to `divdeu`, and has similar advantages to `maddedu`. Modulo result is -available with the quotient. +accumulation affect: `RC` effectively becomes a 64-bit carry in chains +of highly efficient loop-unrolled arbitrary-length big-integer operations. +Similar to `divdeu`, and has similar advantages to `maddedu`, +Modulo result is available with the quotient. **Notes and Observations**: 1. There is no need for an Rc=1 variant as VA-Form is being used. 2. There is no need for Special Registers as VA-Form is being used. +3. Both instructions have been present in Intel x86 for several decades. +4. Neither instruction is present in VSX: these are 128/64 whereas + VSX is 128/128. +5. `maddedu` and `divmod2du` are inverses of each other, including + when used for arbitrary-length big-integer arithmetic **Changes** -- 2.30.2