From 8a2480526f2ff80cbdf0f0f4279e8989b53b6e9b Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 12 Aug 2019 12:19:25 -0700
Subject: [PATCH] Fix $lut pin ordering inside $__ICE40_CARRY_WRAPPER

---
 techlibs/ice40/cells_map.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/techlibs/ice40/cells_map.v b/techlibs/ice40/cells_map.v
index 0c10c9ac4..662423f0a 100644
--- a/techlibs/ice40/cells_map.v
+++ b/techlibs/ice40/cells_map.v
@@ -75,7 +75,7 @@ module \$__ICE40_CARRY_WRAPPER (output CO, O, input A, B, CI, I0, I3);
     .WIDTH(4),
     .LUT(LUT)
   ) lut (
-    .A({I3,B,A,I0}),
+    .A({I0,A,B,I3}),
     .Y(O)
   );
 endmodule
-- 
2.30.2