From 8a319f43c4cb812049e062061b92949b42a57399 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 6 May 2021 18:52:24 +0100 Subject: [PATCH] pass relevant predicate mask bits through to Decoders (PowerDecoderSubset) at the right time --- src/soc/simple/issuer.py | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py index 44bf3b68..0305624c 100644 --- a/src/soc/simple/issuer.py +++ b/src/soc/simple/issuer.py @@ -723,6 +723,11 @@ class TestIssuerInternal(Elaboratable): # proceed to Decode m.next = "DECODE_SV" + # pass predicate mask bits through to satellite decoders + # TODO: for SIMD this will be *multiple* bits + sync += core.sv_pred_sm.eq(self.srcmask[0]) + sync += core.sv_pred_dm.eq(self.dstmask[0]) + # after src/dst step have been updated, we are ready # to decode the instruction with m.State("DECODE_SV"): @@ -735,10 +740,6 @@ class TestIssuerInternal(Elaboratable): sync += core.sv_rm.eq(pdecode2.sv_rm) # set RA_OR_ZERO detection in satellite decoders sync += core.sv_a_nz.eq(pdecode2.sv_a_nz) - # pass predicate mask bits through to satellite decoders - # TODO: for SIMD this will be *multiple* bits - sync += core.sv_pred_sm.eq(self.srcmask[0]) - sync += core.sv_pred_dm.eq(self.dstmask[0]) m.next = "INSN_EXECUTE" # move to "execute" -- 2.30.2