From 8a394f9159664c22e9b4d3c27720f4117cb66614 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 22 Dec 2011 00:04:53 +0100 Subject: [PATCH] verilog: comb reset --- migen/fhdl/verilog.py | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py index 77a766d6..fded9705 100644 --- a/migen/fhdl/verilog.py +++ b/migen/fhdl/verilog.py @@ -119,6 +119,16 @@ def _printcomb(f, ns): r += syn_on + "\n" r += "always @(*) begin\n" + to_reset = list_targets(f.comb) + # do not reset signals with obvious unconditional assignments + for s in f.comb.l: + if isinstance(s, _Assign) and isinstance(s.l, Signal): + try: + to_reset.remove(s.l) + except KeyError: + pass + for t in to_reset: + r += "\t" + ns.get_name(t) + " <= " + str(t.reset) + ";\n" r += _printnode(ns, False, 1, f.comb) r += syn_off r += "\t" + ns.get_name(dummy_d) + " <= " + ns.get_name(dummy_s) + ";\n" -- 2.30.2