From 8a4b5404f3e6ab1b90d44a6c9808f0c71a55970a Mon Sep 17 00:00:00 2001 From: =?utf8?q?Jonathan=20Neusch=C3=A4fer?= Date: Sun, 1 Aug 2021 19:08:50 +0200 Subject: [PATCH] soc.simple.test: Rename setup_test_memory to avoid nosetest calling it --- src/soc/fu/compunits/test/test_compunit.py | 4 ++-- src/soc/simple/test/test_core.py | 4 ++-- src/soc/simple/test/test_microwatt.py | 4 ++-- src/soc/simple/test/test_runner.py | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/soc/fu/compunits/test/test_compunit.py b/src/soc/fu/compunits/test/test_compunit.py index 11eb8b3c..2ce9f2d0 100644 --- a/src/soc/fu/compunits/test/test_compunit.py +++ b/src/soc/fu/compunits/test/test_compunit.py @@ -137,7 +137,7 @@ def get_l0_mem(l0): # BLECH! this is awful! hunting around through structures return mem.mem -def setup_test_memory(l0, sim): +def setup_tst_memory(l0, sim): mem = get_l0_mem(l0) print("before, init mem", mem.depth, mem.width, mem) for i in range(mem.depth): @@ -199,7 +199,7 @@ class TestRunner(FHDLTestCase): # initialise memory if self.funit == Function.LDST: - yield from setup_test_memory(l0, sim) + yield from setup_tst_memory(l0, sim) pc = sim.pc.CIA.value index = pc//4 diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py index 2f588f26..194c0075 100644 --- a/src/soc/simple/test/test_core.py +++ b/src/soc/simple/test/test_core.py @@ -25,7 +25,7 @@ from openpower.endian import bigendian from soc.simple.core import NonProductionCore from soc.experiment.compalu_multi import find_ok # hack -from soc.fu.compunits.test.test_compunit import (setup_test_memory, +from soc.fu.compunits.test.test_compunit import (setup_tst_memory, check_sim_memory) # test with ALU data and Logical data @@ -278,7 +278,7 @@ class TestRunner(FHDLTestCase): gen = program.generate_instructions() instructions = list(zip(gen, program.assembly.splitlines())) - yield from setup_test_memory(l0, sim) + yield from setup_tst_memory(l0, sim) yield from setup_regs(core, test) index = sim.pc.CIA.value//4 diff --git a/src/soc/simple/test/test_microwatt.py b/src/soc/simple/test/test_microwatt.py index b89867e4..15b0659d 100644 --- a/src/soc/simple/test/test_microwatt.py +++ b/src/soc/simple/test/test_microwatt.py @@ -15,7 +15,7 @@ from soc.config.test.test_loadstore import TestMemPspec from soc.simple.test.test_core import (setup_regs, check_regs, wait_for_busy_clear, wait_for_busy_hi) -from soc.fu.compunits.test.test_compunit import (setup_test_memory, +from soc.fu.compunits.test.test_compunit import (setup_tst_memory, check_sim_memory, get_l0_mem) @@ -112,7 +112,7 @@ class TestRunner(FHDLTestCase): # blech! put the same listing into the data memory data_mem = get_l0_mem(l0) yield from setup_i_memory(data_mem, pc, instructions) - # yield from setup_test_memory(l0, sim) + # yield from setup_tst_memory(l0, sim) yield from setup_regs(core, test) yield pc_i.eq(pc) diff --git a/src/soc/simple/test/test_runner.py b/src/soc/simple/test/test_runner.py index fee84617..c7bc9a11 100644 --- a/src/soc/simple/test/test_runner.py +++ b/src/soc/simple/test/test_runner.py @@ -28,7 +28,7 @@ from soc.config.test.test_loadstore import TestMemPspec from soc.simple.test.test_core import (setup_regs, check_regs, wait_for_busy_clear, wait_for_busy_hi) -from soc.fu.compunits.test.test_compunit import (setup_test_memory, +from soc.fu.compunits.test.test_compunit import (setup_tst_memory, check_sim_memory) from soc.debug.dmi import DBGCore, DBGCtrl, DBGStat from nmutil.util import wrap @@ -230,7 +230,7 @@ class TestRunner(FHDLTestCase): counter = 0 # test to pause/start yield from setup_i_memory(imem, pc, instructions) - yield from setup_test_memory(l0, sim) + yield from setup_tst_memory(l0, sim) yield from setup_regs(pdecode2, core, test) # set PC and SVSTATE -- 2.30.2