From 8a607ea0122bd043125f3318bbc6ef1294255e1b Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 12 Apr 2023 14:28:30 +0100 Subject: [PATCH] add section prohibiting cross-over between CR0-7 group and CR8-127 group https://bugs.libre-soc.org/show_bug.cgi?id=1053 --- openpower/sv/svp64.mdwn | 62 ++++++++++++++++++++++++++++++++++++----- 1 file changed, 55 insertions(+), 7 deletions(-) diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn index f662ba2a4..05f48b074 100644 --- a/openpower/sv/svp64.mdwn +++ b/openpower/sv/svp64.mdwn @@ -493,13 +493,13 @@ This is part of `scalar identity behaviour` described above. **Condition Register(s)** -The Scalar Power ISA Condition Register is a 64 bit register where the top -32 MSBs (numbered 0:31 in MSB0 numbering) are not used. This convention is -*preserved* -in SVP64 and an additional 15 Condition Registers provided in -order to store the new CR Fields, CR8-CR15, CR16-CR23 etc. sequentially. -The top 32 MSBs in each new SVP64 Condition Register are *also* not used: -only the bottom 32 bits (numbered 32:63 in MSB0 numbering). +The Scalar Power ISA Condition Register is a 64 bit register where +the top 32 MSBs (numbered 0:31 in MSB0 numbering) are not used. +This convention is *preserved* in SVP64 and an additional 15 Condition +Registers provided in order to store the new CR Fields, CR8-CR15, +CR16-CR23 etc. sequentially. The top 32 MSBs in each new SVP64 Condition +Register are *also* not used: only the bottom 32 bits (numbered 32:63 +in MSB0 numbering). *Programmer's note: using `sv.mfcr` without element-width overrides to take into account the fact that the top 32 MSBs are zero and thus @@ -519,6 +519,54 @@ Condition-Register instructions because all other CR instructions, on closer investigation, will be observed to all be CR-bit or CR-Field related. Thus a `VL` of 16 must be used* +**Condition Register Fields as Predicate Masks** + +Condition Register Fields perform an additional duty in Simple-V: they are +used for Predicate Masks. ARM's Scalar Instruction Set calls single-bit +predication "Conditional Execution", and utilises Condition Codes for +exactly this purpose to solve the problem caused by Branch Speculation. +In a Vector ISA context the concept of Predication is naturally extended +from single-bit to multi-bit, and the (well-known) benefits become all the +more critical given that parallel branches in Vector ISAs are impossible +(even a Vector ISA can only have Scalar branches). + +However the Scalar Power ISA does not have Conditional Execution (for +which, if it had ever been considered, Condition Register bits would be +a perfect natural fit). Thus, when adding Predication using CR Fields +via Simple-V it becomes a somewhat disruptive addition to the Power ISA. + +To ameliorate this situation, particularly for pre-existing Hardware +designs implementing up to Scalar Power ISA v3.1, some rules are set that +allow those pre-existing designs not to require heavy modification to +their existing Scalar pipelines. These rules effectively allow Hardware +Architects to add the additional CR Fields CR8 to CR127 as if they were +an **entirely separate register file**. + +* any instruction involving more than 1 source 1 destination + where one of the operands is a Condition Register is prohibited from + using registers from both the CR0-7 group and the CR8-127 group at + the same time. +* any instruction involving 1 source 1 destination where either the + source or the destination is a Condition Register is prohibited + from setting CR0-7 as a Vector. +* prohibitions are required to be enforced by raising Illegal Instruction + Traps + +Examples of permitted instructions: + +``` + sv.crand *cr8.eq, *cr16.le, *cr40.so # all CR8-CR127 + sv.mfcr cr5, *cr40 # only one source (CR40) copied to CR5 + sv.mfcr *cr16, cr40 # Vector-Splat CR40 onto CR16,17,18... +``` + +Examples of prohibited instructions: + +``` + sv.mfcr *cr0, cr40 # Vector-Splat onto CR0,1,2 + sv.crand cr7, cr9, cr10 # crosses over between CR0-7 and CR8-127 +``` + ## Future expansion. With the way that EXTRA fields are defined and applied to register -- 2.30.2