From 8a690593f4f4980df3fc5f4609674b1e3e62b1bc Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Mon, 11 Dec 2017 13:20:07 +0000 Subject: [PATCH] arch-arm: Using explicit invalidation in TLB When setting TLB related MiscRegs, using explicit TLB regs invalidation rather than implicit switch-case fallthrough Change-Id: Ia1a7358b6d54dda3811be1c5ce5d676f8c518c4d Signed-off-by: Giacomo Travaglini Reviewed-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/10041 Maintainer: Andreas Sandberg --- src/arch/arm/isa.cc | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 899cda9b5..dfd523cf1 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2016 ARM Limited + * Copyright (c) 2010-2017 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -1695,8 +1695,11 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) } else { newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask)); } + // Invalidate TLB MiscReg + getITBPtr(tc)->invalidateMiscReg(); + getDTBPtr(tc)->invalidateMiscReg(); + break; } - M5_FALLTHROUGH; case MISCREG_TTBR0: case MISCREG_TTBR1: { @@ -1709,15 +1712,12 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) newVal = (newVal & (~ttbrMask)); } } - } - M5_FALLTHROUGH; - case MISCREG_SCTLR_EL1: - { + // Invalidate TLB MiscReg getITBPtr(tc)->invalidateMiscReg(); getDTBPtr(tc)->invalidateMiscReg(); - setMiscRegNoEffect(misc_reg, newVal); + break; } - M5_FALLTHROUGH; + case MISCREG_SCTLR_EL1: case MISCREG_CONTEXTIDR: case MISCREG_PRRR: case MISCREG_NMRR: -- 2.30.2