From 8a6ef76052f2d275e86bec08c16db3cfea263f5c Mon Sep 17 00:00:00 2001 From: Alexander Ivchenko Date: Fri, 27 Dec 2013 14:22:35 +0000 Subject: [PATCH] sse.md (3): Extend to support EVEX's SAE mode. * config/i386/sse.md (3): Extend to support EVEX's SAE mode. (*3_finite): Ditto. (*3): Ditto. (avx512f_cmp3): Ditto. (avx512f_vmcmp3): Ditto. (avx512f_vmcmp3_mask): Ditto. (_comi): Ditto. (_ucomi): Ditto. (sse_cvttss2si): Ditto. (sse_cvttss2siq): Ditto. (fix_truncv16sfv16si2): Ditto. (avx512f_vcvttss2usi): Ditto. (avx512f_vcvttss2usiq): Ditto. (avx512f_vcvttsd2usi): Ditto. (avx512f_vcvttsd2usiq): Ditto. (sse2_cvttsd2si): Ditto. (sse2_cvttsd2siq): Ditto. (fix_truncv8dfv8si2): Ditto. (_cvtps2pd): Ditto. (avx512f_getexp): Ditto. (avx512f_fixupimm): Ditto. (avx512f_fixupimm_mask): Ditto. (avx512f_sfixupimm): Ditto. (avx512f_sfixupimm_mask): Ditto. (avx512f_rndscale): Ditto. (avx512f_vcvtph2ps512): Ditto. (avx512f_getmant): Ditto. * config/i386/subst.md (round_saeonly_name): New. (round_saeonly_mask_operand2): Ditto. (round_saeonly_mask_operand3): Ditto. (round_saeonly_mask_scalar_operand3): Ditto. (round_saeonly_mask_scalar_operand4): Ditto. (round_saeonly_mask_scalar_merge_operand4): Ditto. (round_saeonly_sd_mask_operand5): Ditto. (round_saeonly_op2): Ditto. (round_saeonly_op4): Ditto. (round_saeonly_op5): Ditto. (round_saeonly_op6): Ditto. (round_saeonly_mask_op2): Ditto. (round_saeonly_mask_op3): Ditto. (round_saeonly_mask_scalar_op3): Ditto. (round_saeonly_mask_scalar_op4): Ditto. (round_saeonly_mask_scalar_merge_op4): Ditto. (round_saeonly_sd_mask_op5): Ditto. (round_saeonly_constraint): Ditto. (round_saeonly_constraint2): Ditto. (round_saeonly_nimm_predicate): Ditto. (round_saeonly_mode512bit_condition): Ditto. (round_saeonly): Ditto. Co-Authored-By: Andrey Turetskiy Co-Authored-By: Anna Tikhonova Co-Authored-By: Ilya Tocar Co-Authored-By: Ilya Verbin Co-Authored-By: Kirill Yukhin Co-Authored-By: Maxim Kuznetsov Co-Authored-By: Michael Zolotukhin Co-Authored-By: Sergey Lega From-SVN: r206221 --- gcc/ChangeLog | 61 ++++++++++++++ gcc/config/i386/sse.md | 174 +++++++++++++++++++-------------------- gcc/config/i386/subst.md | 31 +++++++ 3 files changed, 179 insertions(+), 87 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index afc4cc13862..88e65b5cf60 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,64 @@ +2013-12-27 Alexander Ivchenko + Maxim Kuznetsov + Sergey Lega + Anna Tikhonova + Ilya Tocar + Andrey Turetskiy + Ilya Verbin + Kirill Yukhin + Michael Zolotukhin + + * config/i386/sse.md (3): Extend to support + EVEX's SAE mode. + (*3_finite): Ditto. + (*3): Ditto. + (avx512f_cmp3): Ditto. + (avx512f_vmcmp3): Ditto. + (avx512f_vmcmp3_mask): Ditto. + (_comi): Ditto. + (_ucomi): Ditto. + (sse_cvttss2si): Ditto. + (sse_cvttss2siq): Ditto. + (fix_truncv16sfv16si2): Ditto. + (avx512f_vcvttss2usi): Ditto. + (avx512f_vcvttss2usiq): Ditto. + (avx512f_vcvttsd2usi): Ditto. + (avx512f_vcvttsd2usiq): Ditto. + (sse2_cvttsd2si): Ditto. + (sse2_cvttsd2siq): Ditto. + (fix_truncv8dfv8si2): Ditto. + (_cvtps2pd): Ditto. + (avx512f_getexp): Ditto. + (avx512f_fixupimm): Ditto. + (avx512f_fixupimm_mask): Ditto. + (avx512f_sfixupimm): Ditto. + (avx512f_sfixupimm_mask): Ditto. + (avx512f_rndscale): Ditto. + (avx512f_vcvtph2ps512): Ditto. + (avx512f_getmant): Ditto. + * config/i386/subst.md (round_saeonly_name): New. + (round_saeonly_mask_operand2): Ditto. + (round_saeonly_mask_operand3): Ditto. + (round_saeonly_mask_scalar_operand3): Ditto. + (round_saeonly_mask_scalar_operand4): Ditto. + (round_saeonly_mask_scalar_merge_operand4): Ditto. + (round_saeonly_sd_mask_operand5): Ditto. + (round_saeonly_op2): Ditto. + (round_saeonly_op4): Ditto. + (round_saeonly_op5): Ditto. + (round_saeonly_op6): Ditto. + (round_saeonly_mask_op2): Ditto. + (round_saeonly_mask_op3): Ditto. + (round_saeonly_mask_scalar_op3): Ditto. + (round_saeonly_mask_scalar_op4): Ditto. + (round_saeonly_mask_scalar_merge_op4): Ditto. + (round_saeonly_sd_mask_op5): Ditto. + (round_saeonly_constraint): Ditto. + (round_saeonly_constraint2): Ditto. + (round_saeonly_nimm_predicate): Ditto. + (round_saeonly_mode512bit_condition): Ditto. + (round_saeonly): Ditto. + 2013-12-27 Alexander Ivchenko Maxim Kuznetsov Sergey Lega diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 4c9f310594e..59eedf42522 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -1566,45 +1566,45 @@ ;; isn't really correct, as those rtl operators aren't defined when ;; applied to NaNs. Hopefully the optimizers won't get too smart on us. -(define_expand "3" +(define_expand "3" [(set (match_operand:VF 0 "register_operand") (smaxmin:VF - (match_operand:VF 1 "nonimmediate_operand") - (match_operand:VF 2 "nonimmediate_operand")))] - "TARGET_SSE && " + (match_operand:VF 1 "") + (match_operand:VF 2 "")))] + "TARGET_SSE && && " { if (!flag_finite_math_only) operands[1] = force_reg (mode, operands[1]); ix86_fixup_binary_operands_no_copy (, mode, operands); }) -(define_insn "*3_finite" +(define_insn "*3_finite" [(set (match_operand:VF 0 "register_operand" "=x,v") (smaxmin:VF - (match_operand:VF 1 "nonimmediate_operand" "%0,v") - (match_operand:VF 2 "nonimmediate_operand" "xm,vm")))] + (match_operand:VF 1 "" "%0,v") + (match_operand:VF 2 "" "xm,")))] "TARGET_SSE && flag_finite_math_only && ix86_binary_operator_ok (, mode, operands) - && " + && && " "@ \t{%2, %0|%0, %2} - v\t{%2, %1, %0|%0, %1, %2}" + v\t{%2, %1, %0|%0, %1, %2}" [(set_attr "isa" "noavx,avx") (set_attr "type" "sseadd") (set_attr "btver2_sse_attr" "maxmin") (set_attr "prefix" "") (set_attr "mode" "")]) -(define_insn "*3" +(define_insn "*3" [(set (match_operand:VF 0 "register_operand" "=x,v") (smaxmin:VF (match_operand:VF 1 "register_operand" "0,v") - (match_operand:VF 2 "nonimmediate_operand" "xm,vm")))] + (match_operand:VF 2 "" "xm,")))] "TARGET_SSE && !flag_finite_math_only - && " + && && " "@ \t{%2, %0|%0, %2} - v\t{%2, %1, %0|%0, %1, %2}" + v\t{%2, %1, %0|%0, %1, %2}" [(set_attr "isa" "noavx,avx") (set_attr "type" "sseadd") (set_attr "btver2_sse_attr" "maxmin") @@ -2142,15 +2142,15 @@ [(V16SF "const_0_to_31_operand") (V8DF "const_0_to_31_operand") (V16SI "const_0_to_7_operand") (V8DI "const_0_to_7_operand")]) -(define_insn "avx512f_cmp3" +(define_insn "avx512f_cmp3" [(set (match_operand: 0 "register_operand" "=k") (unspec: [(match_operand:VI48F_512 1 "register_operand" "v") - (match_operand:VI48F_512 2 "nonimmediate_operand" "vm") + (match_operand:VI48F_512 2 "" "") (match_operand:SI 3 "" "n")] UNSPEC_PCMP))] - "TARGET_AVX512F" - "vcmp\t{%3, %2, %1, %0|%0, %1, %2, %3}" + "TARGET_AVX512F && " + "vcmp\t{%3, %2, %1, %0|%0, %1, %2, %3}" [(set_attr "type" "ssecmp") (set_attr "length_immediate" "1") (set_attr "prefix" "evex") @@ -2170,35 +2170,35 @@ (set_attr "prefix" "evex") (set_attr "mode" "")]) -(define_insn "avx512f_vmcmp3" +(define_insn "avx512f_vmcmp3" [(set (match_operand: 0 "register_operand" "=k") (and: (unspec: [(match_operand:VF_128 1 "register_operand" "v") - (match_operand:VF_128 2 "nonimmediate_operand" "vm") + (match_operand:VF_128 2 "" "") (match_operand:SI 3 "const_0_to_31_operand" "n")] UNSPEC_PCMP) (const_int 1)))] "TARGET_AVX512F" - "vcmp\t{%3, %2, %1, %0|%0, %1, %2, %3}" + "vcmp\t{%3, %2, %1, %0|%0, %1, %2, %3}" [(set_attr "type" "ssecmp") (set_attr "length_immediate" "1") (set_attr "prefix" "evex") (set_attr "mode" "")]) -(define_insn "avx512f_vmcmp3_mask" +(define_insn "avx512f_vmcmp3_mask" [(set (match_operand: 0 "register_operand" "=k") (and: (unspec: [(match_operand:VF_128 1 "register_operand" "v") - (match_operand:VF_128 2 "nonimmediate_operand" "vm") + (match_operand:VF_128 2 "" "") (match_operand:SI 3 "const_0_to_31_operand" "n")] UNSPEC_PCMP) (and: (match_operand: 4 "register_operand" "k") (const_int 1))))] "TARGET_AVX512F" - "vcmp\t{%3, %2, %1, %0%{%4%}|%0%{%4%}, %1, %2, %3}" + "vcmp\t{%3, %2, %1, %0%{%4%}|%0%{%4%}, %1, %2, %3}" [(set_attr "type" "ssecmp") (set_attr "length_immediate" "1") (set_attr "prefix" "evex") @@ -2216,17 +2216,17 @@ (set_attr "prefix" "evex") (set_attr "mode" "")]) -(define_insn "_comi" +(define_insn "_comi" [(set (reg:CCFP FLAGS_REG) (compare:CCFP (vec_select:MODEF (match_operand: 0 "register_operand" "v") (parallel [(const_int 0)])) (vec_select:MODEF - (match_operand: 1 "nonimmediate_operand" "vm") + (match_operand: 1 "" "") (parallel [(const_int 0)]))))] "SSE_FLOAT_MODE_P (mode)" - "%vcomi\t{%1, %0|%0, %1}" + "%vcomi\t{%1, %0|%0, %1}" [(set_attr "type" "ssecomi") (set_attr "prefix" "maybe_vex") (set_attr "prefix_rep" "0") @@ -2236,17 +2236,17 @@ (const_string "0"))) (set_attr "mode" "")]) -(define_insn "_ucomi" +(define_insn "_ucomi" [(set (reg:CCFPU FLAGS_REG) (compare:CCFPU (vec_select:MODEF (match_operand: 0 "register_operand" "v") (parallel [(const_int 0)])) (vec_select:MODEF - (match_operand: 1 "nonimmediate_operand" "vm") + (match_operand: 1 "" "") (parallel [(const_int 0)]))))] "SSE_FLOAT_MODE_P (mode)" - "%vucomi\t{%1, %0|%0, %1}" + "%vucomi\t{%1, %0|%0, %1}" [(set_attr "type" "ssecomi") (set_attr "prefix" "maybe_vex") (set_attr "prefix_rep" "0") @@ -3407,14 +3407,14 @@ (set_attr "prefix" "maybe_vex") (set_attr "mode" "DI")]) -(define_insn "sse_cvttss2si" +(define_insn "sse_cvttss2si" [(set (match_operand:SI 0 "register_operand" "=r,r") (fix:SI (vec_select:SF - (match_operand:V4SF 1 "nonimmediate_operand" "v,m") + (match_operand:V4SF 1 "" "v,") (parallel [(const_int 0)]))))] "TARGET_SSE" - "%vcvttss2si\t{%1, %0|%0, %k1}" + "%vcvttss2si\t{%1, %0|%0, %k1}" [(set_attr "type" "sseicvt") (set_attr "athlon_decode" "double,vector") (set_attr "amdfam10_decode" "double,double") @@ -3423,14 +3423,14 @@ (set_attr "prefix" "maybe_vex") (set_attr "mode" "SI")]) -(define_insn "sse_cvttss2siq" +(define_insn "sse_cvttss2siq" [(set (match_operand:DI 0 "register_operand" "=r,r") (fix:DI (vec_select:SF - (match_operand:V4SF 1 "nonimmediate_operand" "v,vm") + (match_operand:V4SF 1 "" "v,") (parallel [(const_int 0)]))))] "TARGET_SSE && TARGET_64BIT" - "%vcvttss2si{q}\t{%1, %0|%0, %k1}" + "%vcvttss2si{q}\t{%1, %0|%0, %k1}" [(set_attr "type" "sseicvt") (set_attr "athlon_decode" "double,vector") (set_attr "amdfam10_decode" "double,double") @@ -3539,12 +3539,12 @@ (set_attr "prefix" "evex") (set_attr "mode" "XI")]) -(define_insn "fix_truncv16sfv16si2" +(define_insn "fix_truncv16sfv16si2" [(set (match_operand:V16SI 0 "register_operand" "=v") (any_fix:V16SI - (match_operand:V16SF 1 "nonimmediate_operand" "vm")))] + (match_operand:V16SF 1 "" "")))] "TARGET_AVX512F" - "vcvttps2dq\t{%1, %0|%0, %1}" + "vcvttps2dq\t{%1, %0|%0, %1}" [(set_attr "type" "ssecvt") (set_attr "prefix" "evex") (set_attr "mode" "XI")]) @@ -3700,26 +3700,26 @@ (set_attr "prefix" "evex") (set_attr "mode" "DI")]) -(define_insn "avx512f_vcvttss2usi" +(define_insn "avx512f_vcvttss2usi" [(set (match_operand:SI 0 "register_operand" "=r") (unsigned_fix:SI (vec_select:SF - (match_operand:V4SF 1 "nonimmediate_operand" "vm") + (match_operand:V4SF 1 "" "") (parallel [(const_int 0)]))))] "TARGET_AVX512F" - "vcvttss2usi\t{%1, %0|%0, %1}" + "vcvttss2usi\t{%1, %0|%0, %1}" [(set_attr "type" "sseicvt") (set_attr "prefix" "evex") (set_attr "mode" "SI")]) -(define_insn "avx512f_vcvttss2usiq" +(define_insn "avx512f_vcvttss2usiq" [(set (match_operand:DI 0 "register_operand" "=r") (unsigned_fix:DI (vec_select:SF - (match_operand:V4SF 1 "nonimmediate_operand" "vm") + (match_operand:V4SF 1 "" "") (parallel [(const_int 0)]))))] "TARGET_AVX512F && TARGET_64BIT" - "vcvttss2usi\t{%1, %0|%0, %1}" + "vcvttss2usi\t{%1, %0|%0, %1}" [(set_attr "type" "sseicvt") (set_attr "prefix" "evex") (set_attr "mode" "DI")]) @@ -3750,26 +3750,26 @@ (set_attr "prefix" "evex") (set_attr "mode" "DI")]) -(define_insn "avx512f_vcvttsd2usi" +(define_insn "avx512f_vcvttsd2usi" [(set (match_operand:SI 0 "register_operand" "=r") (unsigned_fix:SI (vec_select:DF - (match_operand:V2DF 1 "nonimmediate_operand" "vm") + (match_operand:V2DF 1 "" "") (parallel [(const_int 0)]))))] "TARGET_AVX512F" - "vcvttsd2usi\t{%1, %0|%0, %1}" + "vcvttsd2usi\t{%1, %0|%0, %1}" [(set_attr "type" "sseicvt") (set_attr "prefix" "evex") (set_attr "mode" "SI")]) -(define_insn "avx512f_vcvttsd2usiq" +(define_insn "avx512f_vcvttsd2usiq" [(set (match_operand:DI 0 "register_operand" "=r") (unsigned_fix:DI (vec_select:DF - (match_operand:V2DF 1 "nonimmediate_operand" "vm") + (match_operand:V2DF 1 "" "") (parallel [(const_int 0)]))))] "TARGET_AVX512F && TARGET_64BIT" - "vcvttsd2usi\t{%1, %0|%0, %1}" + "vcvttsd2usi\t{%1, %0|%0, %1}" [(set_attr "type" "sseicvt") (set_attr "prefix" "evex") (set_attr "mode" "DI")]) @@ -3835,14 +3835,14 @@ (set_attr "prefix" "maybe_vex") (set_attr "mode" "DI")]) -(define_insn "sse2_cvttsd2si" +(define_insn "sse2_cvttsd2si" [(set (match_operand:SI 0 "register_operand" "=r,r") (fix:SI (vec_select:DF - (match_operand:V2DF 1 "nonimmediate_operand" "v,m") + (match_operand:V2DF 1 "" "v,") (parallel [(const_int 0)]))))] "TARGET_SSE2" - "%vcvttsd2si\t{%1, %0|%0, %q1}" + "%vcvttsd2si\t{%1, %0|%0, %q1}" [(set_attr "type" "sseicvt") (set_attr "athlon_decode" "double,vector") (set_attr "amdfam10_decode" "double,double") @@ -3852,14 +3852,14 @@ (set_attr "prefix" "maybe_vex") (set_attr "mode" "SI")]) -(define_insn "sse2_cvttsd2siq" +(define_insn "sse2_cvttsd2siq" [(set (match_operand:DI 0 "register_operand" "=r,r") (fix:DI (vec_select:DF - (match_operand:V2DF 1 "nonimmediate_operand" "v,m") + (match_operand:V2DF 1 "" "v,") (parallel [(const_int 0)]))))] "TARGET_SSE2 && TARGET_64BIT" - "%vcvttsd2si{q}\t{%1, %0|%0, %q1}" + "%vcvttsd2si{q}\t{%1, %0|%0, %q1}" [(set_attr "type" "sseicvt") (set_attr "athlon_decode" "double,vector") (set_attr "amdfam10_decode" "double,double") @@ -4019,12 +4019,12 @@ (set_attr "prefix" "evex") (set_attr "mode" "OI")]) -(define_insn "fix_truncv8dfv8si2" +(define_insn "fix_truncv8dfv8si2" [(set (match_operand:V8SI 0 "register_operand" "=v") (any_fix:V8SI - (match_operand:V8DF 1 "nonimmediate_operand" "vm")))] + (match_operand:V8DF 1 "" "")))] "TARGET_AVX512F" - "vcvttpd2dq\t{%1, %0|%0, %1}" + "vcvttpd2dq\t{%1, %0|%0, %1}" [(set_attr "type" "ssecvt") (set_attr "prefix" "evex") (set_attr "mode" "OI")]) @@ -4185,12 +4185,12 @@ (define_mode_attr sf2dfmode [(V8DF "V8SF") (V4DF "V4SF")]) -(define_insn "_cvtps2pd" +(define_insn "_cvtps2pd" [(set (match_operand:VF2_512_256 0 "register_operand" "=v") (float_extend:VF2_512_256 - (match_operand: 1 "nonimmediate_operand" "vm")))] - "TARGET_AVX && " - "vcvtps2pd\t{%1, %0|%0, %1}" + (match_operand: 1 "" "")))] + "TARGET_AVX && && " + "vcvtps2pd\t{%1, %0|%0, %1}" [(set_attr "type" "ssecvt") (set_attr "prefix" "maybe_vex") (set_attr "mode" "")]) @@ -6560,12 +6560,12 @@ (set_attr "prefix" "evex") (set_attr "mode" "")]) -(define_insn "avx512f_getexp" +(define_insn "avx512f_getexp" [(set (match_operand:VF_512 0 "register_operand" "=v") - (unspec:VF_512 [(match_operand:VF_512 1 "nonimmediate_operand" "vm")] + (unspec:VF_512 [(match_operand:VF_512 1 "" "")] UNSPEC_GETEXP))] "TARGET_AVX512F" - "vgetexp\t{%1, %0|%0, %1}"; + "vgetexp\t{%1, %0|%0, %1}"; [(set_attr "prefix" "evex") (set_attr "mode" "")]) @@ -6641,32 +6641,32 @@ DONE; }) -(define_insn "avx512f_fixupimm" +(define_insn "avx512f_fixupimm" [(set (match_operand:VF_512 0 "register_operand" "=v") (unspec:VF_512 [(match_operand:VF_512 1 "register_operand" "0") (match_operand:VF_512 2 "register_operand" "v") - (match_operand: 3 "nonimmediate_operand" "vm") + (match_operand: 3 "" "") (match_operand:SI 4 "const_0_to_255_operand")] UNSPEC_FIXUPIMM))] "TARGET_AVX512F" - "vfixupimm\t{%4, %3, %2, %0|%0, %2, %3, %4}"; + "vfixupimm\t{%4, %3, %2, %0|%0, %2, %3, %4}"; [(set_attr "prefix" "evex") (set_attr "mode" "")]) -(define_insn "avx512f_fixupimm_mask" +(define_insn "avx512f_fixupimm_mask" [(set (match_operand:VF_512 0 "register_operand" "=v") (vec_merge:VF_512 (unspec:VF_512 [(match_operand:VF_512 1 "register_operand" "0") (match_operand:VF_512 2 "register_operand" "v") - (match_operand: 3 "nonimmediate_operand" "vm") + (match_operand: 3 "" "") (match_operand:SI 4 "const_0_to_255_operand")] UNSPEC_FIXUPIMM) (match_dup 1) (match_operand: 5 "register_operand" "k")))] "TARGET_AVX512F" - "vfixupimm\t{%4, %3, %2, %0%{%5%}|%0%{%5%}, %2, %3, %4}"; + "vfixupimm\t{%4, %3, %2, %0%{%5%}|%0%{%5%}, %2, %3, %4}"; [(set_attr "prefix" "evex") (set_attr "mode" "")]) @@ -6685,30 +6685,30 @@ DONE; }) -(define_insn "avx512f_sfixupimm" +(define_insn "avx512f_sfixupimm" [(set (match_operand:VF_128 0 "register_operand" "=v") (vec_merge:VF_128 (unspec:VF_128 [(match_operand:VF_128 1 "register_operand" "0") (match_operand:VF_128 2 "register_operand" "v") - (match_operand: 3 "nonimmediate_operand" "vm") + (match_operand: 3 "" "") (match_operand:SI 4 "const_0_to_255_operand")] UNSPEC_FIXUPIMM) (match_dup 1) (const_int 1)))] "TARGET_AVX512F" - "vfixupimm\t{%4, %3, %2, %0|%0, %2, %3, %4}"; + "vfixupimm\t{%4, %3, %2, %0|%0, %2, %3, %4}"; [(set_attr "prefix" "evex") (set_attr "mode" "")]) -(define_insn "avx512f_sfixupimm_mask" +(define_insn "avx512f_sfixupimm_mask" [(set (match_operand:VF_128 0 "register_operand" "=v") (vec_merge:VF_128 (vec_merge:VF_128 (unspec:VF_128 [(match_operand:VF_128 1 "register_operand" "0") (match_operand:VF_128 2 "register_operand" "v") - (match_operand: 3 "nonimmediate_operand" "vm") + (match_operand: 3 "" "") (match_operand:SI 4 "const_0_to_255_operand")] UNSPEC_FIXUPIMM) (match_dup 1) @@ -6716,18 +6716,18 @@ (match_dup 1) (match_operand: 5 "register_operand" "k")))] "TARGET_AVX512F" - "vfixupimm\t{%4, %3, %2, %0%{%5%}|%0%{%5%}, %2, %3, %4}"; + "vfixupimm\t{%4, %3, %2, %0%{%5%}|%0%{%5%}, %2, %3, %4}"; [(set_attr "prefix" "evex") (set_attr "mode" "")]) -(define_insn "avx512f_rndscale" +(define_insn "avx512f_rndscale" [(set (match_operand:VF_512 0 "register_operand" "=v") (unspec:VF_512 - [(match_operand:VF_512 1 "nonimmediate_operand" "vm") + [(match_operand:VF_512 1 "" "") (match_operand:SI 2 "const_0_to_255_operand")] UNSPEC_ROUND))] "TARGET_AVX512F" - "vrndscale\t{%2, %1, %0|%0, %1, %2}" + "vrndscale\t{%2, %1, %0|%0, %1, %2}" [(set_attr "length_immediate" "1") (set_attr "prefix" "evex") (set_attr "mode" "")]) @@ -14602,13 +14602,13 @@ (set_attr "btver2_decode" "double") (set_attr "mode" "V8SF")]) -(define_insn "avx512f_vcvtph2ps512" +(define_insn "avx512f_vcvtph2ps512" [(set (match_operand:V16SF 0 "register_operand" "=v") (unspec:V16SF - [(match_operand:V16HI 1 "nonimmediate_operand" "vm")] + [(match_operand:V16HI 1 "" "")] UNSPEC_VCVTPH2PS))] "TARGET_AVX512F" - "vcvtph2ps\t{%1, %0|%0, %1}" + "vcvtph2ps\t{%1, %0|%0, %1}" [(set_attr "type" "ssecvt") (set_attr "prefix" "evex") (set_attr "mode" "V16SF")]) @@ -15107,14 +15107,14 @@ (set_attr "memory" "none,load") (set_attr "mode" "")]) -(define_insn "avx512f_getmant" +(define_insn "avx512f_getmant" [(set (match_operand:VF_512 0 "register_operand" "=v") (unspec:VF_512 - [(match_operand:VF_512 1 "nonimmediate_operand" "vm") + [(match_operand:VF_512 1 "" "") (match_operand:SI 2 "const_0_to_15_operand")] UNSPEC_GETMANT))] "TARGET_AVX512F" - "vgetmant\t{%2, %1, %0|%0, %1, %2}"; + "vgetmant\t{%2, %1, %0|%0, %1, %2}"; [(set_attr "prefix" "evex") (set_attr "mode" "")]) diff --git a/gcc/config/i386/subst.md b/gcc/config/i386/subst.md index b20cf20f95d..d17b8b263ed 100644 --- a/gcc/config/i386/subst.md +++ b/gcc/config/i386/subst.md @@ -129,3 +129,34 @@ (set (match_dup 0) (match_dup 1)) (unspec [(match_operand:SI 2 "const_0_to_4_operand")] UNSPEC_EMBEDDED_ROUNDING)])]) + +(define_subst_attr "round_saeonly_name" "round_saeonly" "" "_round") +(define_subst_attr "round_saeonly_mask_operand2" "mask" "%R2" "%R4") +(define_subst_attr "round_saeonly_mask_operand3" "mask" "%R3" "%R5") +(define_subst_attr "round_saeonly_mask_scalar_operand3" "mask_scalar" "%R3" "%R5") +(define_subst_attr "round_saeonly_mask_scalar_operand4" "mask_scalar" "%R4" "%R6") +(define_subst_attr "round_saeonly_mask_scalar_merge_operand4" "mask_scalar_merge" "%R4" "%R5") +(define_subst_attr "round_saeonly_sd_mask_operand5" "sd" "%R5" "%R7") +(define_subst_attr "round_saeonly_op2" "round_saeonly" "" "%R2") +(define_subst_attr "round_saeonly_op4" "round_saeonly" "" "%R4") +(define_subst_attr "round_saeonly_op5" "round_saeonly" "" "%R5") +(define_subst_attr "round_saeonly_op6" "round_saeonly" "" "%R6") +(define_subst_attr "round_saeonly_mask_op2" "round_saeonly" "" "") +(define_subst_attr "round_saeonly_mask_op3" "round_saeonly" "" "") +(define_subst_attr "round_saeonly_mask_scalar_op3" "round_saeonly" "" "") +(define_subst_attr "round_saeonly_mask_scalar_op4" "round_saeonly" "" "") +(define_subst_attr "round_saeonly_mask_scalar_merge_op4" "round_saeonly" "" "") +(define_subst_attr "round_saeonly_sd_mask_op5" "round_saeonly" "" "") +(define_subst_attr "round_saeonly_constraint" "round_saeonly" "vm" "v") +(define_subst_attr "round_saeonly_constraint2" "round_saeonly" "m" "v") +(define_subst_attr "round_saeonly_nimm_predicate" "round_saeonly" "nonimmediate_operand" "register_operand") +(define_subst_attr "round_saeonly_mode512bit_condition" "round_saeonly" "1" "(mode == V16SFmode || mode == V8DFmode)") + +(define_subst "round_saeonly" + [(set (match_operand:SUBST_A 0) + (match_operand:SUBST_A 1))] + "TARGET_AVX512F" + [(parallel[ + (set (match_dup 0) + (match_dup 1)) + (unspec [(match_operand:SI 2 "const_4_to_5_operand")] UNSPEC_EMBEDDED_ROUNDING)])]) -- 2.30.2