From 8a8e515c2bf1a48117f463a949174c666932711b Mon Sep 17 00:00:00 2001 From: Jonathan Wright Date: Wed, 27 Jan 2021 12:23:15 +0000 Subject: [PATCH] aarch64: Use RTL builtins for [su]mlsl_n intrinsics Rewrite [su]mlsl_n Neon intrinsics to use RTL builtins rather than inline assembly code, allowing for better scheduling and optimization. gcc/ChangeLog: 2021-01-27 Jonathan Wright * config/aarch64/aarch64-simd-builtins.def: Add [su]mlsl_n builtin generator macros. * config/aarch64/aarch64-simd.md (aarch64_mlsl_n): Define. * config/aarch64/arm_neon.h (vmlsl_n_s16): Use RTL builtin instead of inline asm. (vmlsl_n_s32): Likewise. (vmlsl_n_u16): Likewise. (vmlsl_n_u32): Likewise. --- gcc/config/aarch64/aarch64-simd-builtins.def | 4 +++ gcc/config/aarch64/aarch64-simd.md | 15 +++++++++++ gcc/config/aarch64/arm_neon.h | 28 +++----------------- 3 files changed, 23 insertions(+), 24 deletions(-) diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def index a1db6c75bd2..cb79c08ba66 100644 --- a/gcc/config/aarch64/aarch64-simd-builtins.def +++ b/gcc/config/aarch64/aarch64-simd-builtins.def @@ -198,6 +198,10 @@ BUILTIN_VD_BHSI (TERNOP, smlsl, 0, NONE) BUILTIN_VD_BHSI (TERNOPU, umlsl, 0, NONE) + /* Implemented by aarch64_mlsl_n. */ + BUILTIN_VD_HSI (TERNOP, smlsl_n, 0, NONE) + BUILTIN_VD_HSI (TERNOPU, umlsl_n, 0, NONE) + /* Implemented by aarch64_mlal. */ BUILTIN_VD_BHSI (TERNOP, smlal, 0, NONE) BUILTIN_VD_BHSI (TERNOPU, umlal, 0, NONE) diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 2f6f1cb517c..919d0b03998 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -1961,6 +1961,21 @@ [(set_attr "type" "neon_mla__long")] ) +(define_insn "aarch64_mlsl_n" + [(set (match_operand: 0 "register_operand" "=w") + (minus: + (match_operand: 1 "register_operand" "0") + (mult: + (ANY_EXTEND: + (vec_duplicate:VD_HSI + (match_operand: 3 "register_operand" ""))) + (ANY_EXTEND: + (match_operand:VD_HSI 2 "register_operand" "w")))))] + "TARGET_SIMD" + "mlsl\t%0., %2., %3.[0]" + [(set_attr "type" "neon_mla__long")] +) + (define_insn "aarch64_simd_vec_mult_lo_" [(set (match_operand: 0 "register_operand" "=w") (mult: (ANY_EXTEND: (vec_select: diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h index 8d0178987d7..b56ab68aad5 100644 --- a/gcc/config/aarch64/arm_neon.h +++ b/gcc/config/aarch64/arm_neon.h @@ -8184,48 +8184,28 @@ __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlsl_n_s16 (int32x4_t __a, int16x4_t __b, int16_t __c) { - int32x4_t __result; - __asm__ ("smlsl %0.4s, %2.4h, %3.h[0]" - : "=w"(__result) - : "0"(__a), "w"(__b), "x"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_smlsl_nv4hi (__a, __b, __c); } __extension__ extern __inline int64x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlsl_n_s32 (int64x2_t __a, int32x2_t __b, int32_t __c) { - int64x2_t __result; - __asm__ ("smlsl %0.2d, %2.2s, %3.s[0]" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_smlsl_nv2si (__a, __b, __c); } __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlsl_n_u16 (uint32x4_t __a, uint16x4_t __b, uint16_t __c) { - uint32x4_t __result; - __asm__ ("umlsl %0.4s, %2.4h, %3.h[0]" - : "=w"(__result) - : "0"(__a), "w"(__b), "x"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_umlsl_nv4hi_uuuu (__a, __b, __c); } __extension__ extern __inline uint64x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlsl_n_u32 (uint64x2_t __a, uint32x2_t __b, uint32_t __c) { - uint64x2_t __result; - __asm__ ("umlsl %0.2d, %2.2s, %3.s[0]" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_umlsl_nv2si_uuuu (__a, __b, __c); } __extension__ extern __inline int16x8_t -- 2.30.2