From 8a91315e352146b3ac52ae94886c2372f13be063 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Sat, 7 May 2022 01:58:24 +0100
Subject: [PATCH]

---
 openpower/sv/SimpleV_rationale.mdwn | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index 74d7b4efb..c6589b41a 100644
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -294,7 +294,8 @@ of the problem-space:
   go as low as 8-bit arithmetic, even 8-bit Floating-Point for
   high-performance AI. Rather than waste opcode space adding all
   such operations at different bitwidths, let the prefix
-  *redefine* the element width.
+  *redefine* (override) the element width, without actually altering
+  the Scalar ISA at all.
 * "Reordering" of the assumption of linear sequential element
   access, for Matrices, rotations, transposition, Convolutions,
   DCT, FFT, Parallel Prefix-Sum and other common transformations
-- 
2.30.2