From 8a9e0309baa527b3d360b4f719a7a7ff460d37af Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 12 May 2020 21:21:49 +0100 Subject: [PATCH] add 3rd register input to ALUInputData --- src/soc/alu/pipe_data.py | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/src/soc/alu/pipe_data.py b/src/soc/alu/pipe_data.py index d512dc01..f64a39f9 100644 --- a/src/soc/alu/pipe_data.py +++ b/src/soc/alu/pipe_data.py @@ -20,8 +20,9 @@ class IntegerData: class ALUInputData(IntegerData): def __init__(self, pspec): super().__init__(pspec) - self.a = Signal(64, reset_less=True) - self.b = Signal(64, reset_less=True) + self.a = Signal(64, reset_less=True) # RA + self.b = Signal(64, reset_less=True) # RB/immediate + self.c = Signal(64, reset_less=True) # RC/RS self.so = Signal(reset_less=True) self.carry_in = Signal(reset_less=True) @@ -29,12 +30,13 @@ class ALUInputData(IntegerData): yield from super().__iter__() yield self.a yield self.b + yield self.c yield self.carry_in yield self.so def eq(self, i): lst = super().eq(i) - return lst + [self.a.eq(i.a), self.b.eq(i.b), + return lst + [self.a.eq(i.a), self.b.eq(i.b), self.c.eq(i.c), self.carry_in.eq(i.carry_in), self.so.eq(i.so)] @@ -72,6 +74,7 @@ class ALUOutputData(IntegerData): self.cr0.eq(i.cr0), self.ov.eq(i.ov), self.ov32.eq(i.ov32), self.so.eq(i.so)] + class IntPipeSpec: def __init__(self, id_wid=2, op_wid=1): self.id_wid = id_wid @@ -79,6 +82,7 @@ class IntPipeSpec: self.opkls = lambda _: CompALUOpSubset(name="op") self.stage = None + class ALUPipeSpec(IntPipeSpec): def __init__(self, id_wid, op_wid): super().__init__(id_wid, op_wid) -- 2.30.2