From 8aa67ffdcc63523adbb39c49cab2ea71f9d444d4 Mon Sep 17 00:00:00 2001 From: Cesar Strauss Date: Wed, 21 Apr 2021 14:43:57 -0300 Subject: [PATCH] Add CR predication test case for TestIssuer Directly derived from the corresponding case in test_caller_svp64_predication.py It is expected to fail, until CR predication is implemented on TestIssuer. --- src/soc/fu/alu/test/svp64_cases.py | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/src/soc/fu/alu/test/svp64_cases.py b/src/soc/fu/alu/test/svp64_cases.py index b4bf1f08..72c982fd 100644 --- a/src/soc/fu/alu/test/svp64_cases.py +++ b/src/soc/fu/alu/test/svp64_cases.py @@ -524,3 +524,33 @@ class SVP64ALUTestCase(TestAccumulatorBase): self.add_case(Program(lst, bigendian), initial_regs, initial_svstate=svstate) + + def case_18_sv_add_cr_pred(self): + # adds, CR predicated mask CR4.eq = 1, CR5.eq = 0, invert (ne) + # 1 = 5 + 9 => not to be touched (skipped) + # 2 = 6 + 10 => 0x3334 = 0x2223+0x1111 + # expected results: + # r1 = 0xbeef skipped since CR4 is 1 and test is inverted + # r2 = 0x3334 CR5 is 0, so this is used + isa = SVP64Asm(['sv.add/m=ne 1.v, 5.v, 9.v']) + lst = list(isa) + print("listing", lst) + + # initial values in GPR regfile + initial_regs = [0] * 32 + initial_regs[1] = 0xbeef # not to be altered + initial_regs[9] = 0x1234 + initial_regs[10] = 0x1111 + initial_regs[5] = 0x4321 + initial_regs[6] = 0x2223 + # SVSTATE (in this case, VL=2) + svstate = SVP64State() + svstate.vl[0:7] = 2 # VL + svstate.maxvl[0:7] = 2 # MAXVL + print("SVSTATE", bin(svstate.spr.asint())) + + # set up CR predicate - CR4.eq=1 and CR5.eq=0 + cr = 0b0010 << ((7-4)*4) # CR4.eq (we hope) + + self.add_case(Program(lst, bigendian), initial_regs, + initial_svstate=svstate, initial_cr=cr) -- 2.30.2