From 8ac9e7f81ea6f8434fe9efc454feadfd4e3d2862 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 10 Nov 2021 18:26:15 +0000 Subject: [PATCH] whitespace --- src/soc/fu/mmu/fsm.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/soc/fu/mmu/fsm.py b/src/soc/fu/mmu/fsm.py index e6345df7..1fd0f657 100644 --- a/src/soc/fu/mmu/fsm.py +++ b/src/soc/fu/mmu/fsm.py @@ -131,7 +131,7 @@ class FSMMMUStage(ControlBase): with m.Switch(op.insn_type): with m.Case(MicrOp.OP_MTSPR): - comb += Display("MMUTEST: OP_MTSPR: spr=%i",spr); + comb += Display("MMUTEST: OP_MTSPR: spr=%i", spr) # despite redirection this FU **MUST** behave exactly # like the SPR FU. this **INCLUDES** updating the SPR # regfile because the CSV file entry for OP_MTSPR @@ -166,18 +166,18 @@ class FSMMMUStage(ControlBase): with m.Case(MicrOp.OP_MFSPR): comb += Display("MMUTEST: OP_MFSPR: spr=%i returns=%i", - spr,spr1_i); + spr, spr1_i) comb += o.data.eq(spr1_i) comb += o.ok.eq(1) comb += done.eq(1) with m.Case(MicrOp.OP_TLBIE): - comb += Display("MMUTEST: OP_TLBIE: insn_bits=%i",spr); + comb += Display("MMUTEST: OP_TLBIE: insn_bits=%i", spr) # pass TLBIE request to MMU (spec: v3.0B p1034) # note that the spr is *not* an actual spr number, it's # just that those bits happen to match with field bits # RIC, PRS, R - comb += Display("TLBIE: %i %i",spr,l_out.done) + comb += Display("TLBIE: %i %i", spr, l_out.done) comb += valid.eq(1) # start "pulse" comb += l_in.valid.eq(blip) # start comb += l_in.tlbie.eq(1) # mtspr mode -- 2.30.2