From 8acb38447116aa294da47f17424e329c34eccbd6 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Daniel=20Sch=C3=BCrmann?= Date: Mon, 17 Feb 2020 17:34:45 +0100 Subject: [PATCH] aco: add sub-dword regclasses MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Co-authored-by: Rhys Perry Reviewed-By: Timur Kristóf Part-of: --- src/amd/compiler/aco_ir.h | 32 ++++++++++++++++++++++++++++++- src/amd/compiler/aco_print_ir.cpp | 6 ++++++ 2 files changed, 37 insertions(+), 1 deletion(-) diff --git a/src/amd/compiler/aco_ir.h b/src/amd/compiler/aco_ir.h index c8b5c00e1f2..2679fbdddbd 100644 --- a/src/amd/compiler/aco_ir.h +++ b/src/amd/compiler/aco_ir.h @@ -199,6 +199,13 @@ struct RegClass { v6 = 6 | (1 << 5), v7 = 7 | (1 << 5), v8 = 8 | (1 << 5), + /* byte-sized register class */ + v1b = v1 | (1 << 7), + v2b = v2 | (1 << 7), + v3b = v3 | (1 << 7), + v4b = v4 | (1 << 7), + v6b = v6 | (1 << 7), + v8b = v8 | (1 << 7), /* these are used for WWM and spills to vgpr */ v1_linear = v1 | (1 << 6), v2_linear = v2 | (1 << 6), @@ -214,7 +221,10 @@ struct RegClass { explicit operator bool() = delete; constexpr RegType type() const { return rc <= RC::s16 ? RegType::sgpr : RegType::vgpr; } - constexpr unsigned size() const { return (unsigned) rc & 0x1F; } + constexpr bool is_subdword() const { return rc & (1 << 7); } + constexpr unsigned bytes() const { return ((unsigned) rc & 0x1F) * (is_subdword() ? 1 : 4); } + //TODO: use size() less in favor of bytes() + constexpr unsigned size() const { return (bytes() + 3) >> 2; } constexpr bool is_linear() const { return rc <= RC::s16 || rc & (1 << 6); } constexpr RegClass as_linear() const { return RegClass((RC) (rc | (1 << 6))); } @@ -237,6 +247,12 @@ static constexpr RegClass v5{RegClass::v5}; static constexpr RegClass v6{RegClass::v6}; static constexpr RegClass v7{RegClass::v7}; static constexpr RegClass v8{RegClass::v8}; +static constexpr RegClass v1b{RegClass::v1b}; +static constexpr RegClass v2b{RegClass::v2b}; +static constexpr RegClass v3b{RegClass::v3b}; +static constexpr RegClass v4b{RegClass::v4b}; +static constexpr RegClass v6b{RegClass::v6b}; +static constexpr RegClass v8b{RegClass::v8b}; /** * Temp Class @@ -252,6 +268,7 @@ struct Temp { constexpr uint32_t id() const noexcept { return id_; } constexpr RegClass regClass() const noexcept { return reg_class; } + constexpr unsigned bytes() const noexcept { return reg_class.bytes(); } constexpr unsigned size() const noexcept { return reg_class.size(); } constexpr RegType type() const noexcept { return reg_class.type(); } constexpr bool is_linear() const noexcept { return reg_class.is_linear(); } @@ -433,6 +450,14 @@ public: return data_.temp.regClass(); } + constexpr unsigned bytes() const noexcept + { + if (isConstant()) + return is64BitConst_ ? 8 : 4; //TODO: sub-dword constants + else + return data_.temp.bytes(); + } + constexpr unsigned size() const noexcept { if (isConstant()) @@ -650,6 +675,11 @@ public: return temp.regClass(); } + constexpr unsigned bytes() const noexcept + { + return temp.bytes(); + } + constexpr unsigned size() const noexcept { return temp.size(); diff --git a/src/amd/compiler/aco_print_ir.cpp b/src/amd/compiler/aco_print_ir.cpp index 0f607fe3f68..4b6817b0202 100644 --- a/src/amd/compiler/aco_print_ir.cpp +++ b/src/amd/compiler/aco_print_ir.cpp @@ -54,6 +54,12 @@ static void print_reg_class(const RegClass rc, FILE *output) case RegClass::v6: fprintf(output, " v6: "); return; case RegClass::v7: fprintf(output, " v7: "); return; case RegClass::v8: fprintf(output, " v8: "); return; + case RegClass::v1b: fprintf(output, " v1b: "); return; + case RegClass::v2b: fprintf(output, " v2b: "); return; + case RegClass::v3b: fprintf(output, " v3b: "); return; + case RegClass::v4b: fprintf(output, " v4b: "); return; + case RegClass::v6b: fprintf(output, " v6b: "); return; + case RegClass::v8b: fprintf(output, " v8b: "); return; case RegClass::v1_linear: fprintf(output, " v1: "); return; case RegClass::v2_linear: fprintf(output, " v2: "); return; } -- 2.30.2