From 8acd5a560737f903177374867ce35eb823475108 Mon Sep 17 00:00:00 2001 From: Anton Blanchard Date: Sat, 14 Aug 2021 15:03:16 +1000 Subject: [PATCH] verilator: Specify top level module While verilator finds the correct top level module with the current setup, if we start adding simulation models it can get confused. Explicitly specify the top level module. Signed-off-by: Anton Blanchard --- Makefile | 2 +- verilator/microwatt-verilator.cpp | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/Makefile b/Makefile index 63c0c6f..ca3ee5f 100644 --- a/Makefile +++ b/Makefile @@ -205,7 +205,7 @@ microwatt.v: $(synth_files) $(RAM_INIT_FILE) $(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(synth_files) -e toplevel; write_verilog $@" microwatt-verilator: microwatt.v verilator/microwatt-verilator.cpp verilator/uart-verilator.c - $(VERILATOR) $(VERILATOR_FLAGS) -CFLAGS "$(VERILATOR_CFLAGS) -DCLK_FREQUENCY=$(CLK_FREQUENCY)" -Iuart16550 --assert --cc --exe --build $^ -o $@ + $(VERILATOR) $(VERILATOR_FLAGS) -CFLAGS "$(VERILATOR_CFLAGS) -DCLK_FREQUENCY=$(CLK_FREQUENCY)" -Iuart16550 --assert --cc --exe --build $^ -o $@ -top-module toplevel @cp -f obj_dir/microwatt-verilator microwatt-verilator microwatt_out.config: microwatt.json $(LPF) diff --git a/verilator/microwatt-verilator.cpp b/verilator/microwatt-verilator.cpp index 1e82820..3c37f0a 100644 --- a/verilator/microwatt-verilator.cpp +++ b/verilator/microwatt-verilator.cpp @@ -1,5 +1,5 @@ #include -#include "Vmicrowatt.h" +#include "Vtoplevel.h" #include "verilated.h" #include "verilated_vcd_c.h" @@ -24,7 +24,7 @@ double sc_time_stamp(void) VerilatedVcdC *tfp; #endif -void tick(Vmicrowatt *top) +void tick(Vtoplevel *top) { top->ext_clk = 1; top->eval(); @@ -51,7 +51,7 @@ int main(int argc, char **argv) Verilated::commandArgs(argc, argv); // init top verilog instance - Vmicrowatt* top = new Vmicrowatt; + Vtoplevel* top = new Vtoplevel; #if VM_TRACE // init trace dump -- 2.30.2