From 8ad84323c00dd2da942970d1d7d2e835d584ad40 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Thu, 8 Sep 2022 15:17:19 +0100
Subject: [PATCH]

---
 openpower/sv/rfc/001.mdwn | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/openpower/sv/rfc/001.mdwn b/openpower/sv/rfc/001.mdwn
index 6d5e61cdd..246f14e06 100644
--- a/openpower/sv/rfc/001.mdwn
+++ b/openpower/sv/rfc/001.mdwn
@@ -12,6 +12,7 @@ Links
 * <https://libre-soc.org/openpower/sv/av_opcodes/>
 * <https://libre-soc.org/openpower/sv/fcvt/>
 * <https://libre-soc.org/openpower/sv/cr_int_predication/>
+* <https://libre-soc.org/openpower/sv/biginteger/>
 
 # Introduction to Simple-V
 
@@ -38,6 +39,9 @@ the **Scalar** Power ISA up-to-date.  These include IEEE754 Transcendentals
 AV cryptographic Biginteger and bitmanipulation operations that ARM Intel
 AMD and many other ISAs have been adding over the past 12 years.
 
+*Thus it becomes necesary to consider the Architectural Resource Allocation of not just
+Simple-V but the 80-100 Scalar instructions all at the same time*.
+
 # Resources
 
 
-- 
2.30.2