From 8adc6781bf5741cca9a27e9e2c523b4def5a3bc3 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Thu, 13 Oct 2011 02:22:23 -0700 Subject: [PATCH] X86: Turn on the page table walker in SE mode. --- src/arch/x86/SConscript | 6 ++-- src/arch/x86/X86TLB.py | 17 ++++------ src/arch/x86/tlb.cc | 73 +++++++++++++++++++++-------------------- src/arch/x86/tlb.hh | 6 +--- src/cpu/BaseCPU.py | 3 +- 5 files changed, 50 insertions(+), 55 deletions(-) diff --git a/src/arch/x86/SConscript b/src/arch/x86/SConscript index 1b443cd83..5ac092185 100644 --- a/src/arch/x86/SConscript +++ b/src/arch/x86/SConscript @@ -57,6 +57,7 @@ if env['TARGET_ISA'] == 'x86': Source('isa.cc') Source('nativetrace.cc') Source('pagetable.cc') + Source('pagetable_walker.cc') Source('predecoder.cc') Source('predecoder_tables.cc') Source('remote_gdb.cc') @@ -70,18 +71,17 @@ if env['TARGET_ISA'] == 'x86': DebugFlag('Faults', "Trace all faults/exceptions/traps") DebugFlag('LocalApic', "Local APIC debugging") + DebugFlag('PageTableWalker', \ + "Page table walker state machine debugging") DebugFlag('Predecoder', "Predecoder debug output") DebugFlag('X86', "Generic X86 ISA debugging") if env['FULL_SYSTEM']: - DebugFlag('PageTableWalker', \ - "Page table walker state machine debugging") SimObject('X86System.py') # Full-system sources Source('linux/system.cc') - Source('pagetable_walker.cc') Source('system.cc') Source('stacktrace.cc') Source('vtophys.cc') diff --git a/src/arch/x86/X86TLB.py b/src/arch/x86/X86TLB.py index ae9bfd353..7f2fcd358 100644 --- a/src/arch/x86/X86TLB.py +++ b/src/arch/x86/X86TLB.py @@ -35,24 +35,21 @@ # # Authors: Gabe Black -from m5.defines import buildEnv from m5.params import * from m5.proxy import * from BaseTLB import BaseTLB from MemObject import MemObject -if buildEnv['FULL_SYSTEM']: - class X86PagetableWalker(MemObject): - type = 'X86PagetableWalker' - cxx_class = 'X86ISA::Walker' - port = Port("Port for the hardware table walker") - system = Param.System(Parent.any, "system object") +class X86PagetableWalker(MemObject): + type = 'X86PagetableWalker' + cxx_class = 'X86ISA::Walker' + port = Port("Port for the hardware table walker") + system = Param.System(Parent.any, "system object") class X86TLB(BaseTLB): type = 'X86TLB' cxx_class = 'X86ISA::TLB' size = Param.Int(64, "TLB size") - if buildEnv['FULL_SYSTEM']: - walker = Param.X86PagetableWalker(\ - X86PagetableWalker(), "page table walker") + walker = Param.X86PagetableWalker(\ + X86PagetableWalker(), "page table walker") diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc index 40c30637d..88eb19b54 100644 --- a/src/arch/x86/tlb.cc +++ b/src/arch/x86/tlb.cc @@ -44,6 +44,7 @@ #include "arch/x86/regs/msr.hh" #include "arch/x86/faults.hh" #include "arch/x86/pagetable.hh" +#include "arch/x86/pagetable_walker.hh" #include "arch/x86/tlb.hh" #include "arch/x86/x86_traits.hh" #include "base/bitfield.hh" @@ -55,13 +56,13 @@ #include "mem/packet_access.hh" #include "mem/request.hh" -#if FULL_SYSTEM -#include "arch/x86/pagetable_walker.hh" -#else +#if !FULL_SYSTEM #include "mem/page_table.hh" #include "sim/process.hh" #endif +#include "sim/full_system.hh" + namespace X86ISA { TLB::TLB(const Params *p) : BaseTLB(p), configAddress(0), size(p->size) @@ -72,10 +73,8 @@ TLB::TLB(const Params *p) : BaseTLB(p), configAddress(0), size(p->size) for (int x = 0; x < size; x++) freeList.push_back(&tlb[x]); -#if FULL_SYSTEM walker = p->walker; walker->setTLB(this); -#endif } TlbEntry * @@ -293,40 +292,42 @@ TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation, // The vaddr already has the segment base applied. TlbEntry *entry = lookup(vaddr); if (!entry) { -#if FULL_SYSTEM - Fault fault = walker->start(tc, translation, req, mode); - if (timing || fault != NoFault) { - // This gets ignored in atomic mode. - delayedResponse = true; - return fault; - } - entry = lookup(vaddr); - assert(entry); -#else - DPRINTF(TLB, "Handling a TLB miss for " - "address %#x at pc %#x.\n", - vaddr, tc->instAddr()); - - Process *p = tc->getProcessPtr(); - TlbEntry newEntry; - bool success = p->pTable->lookup(vaddr, newEntry); - if (!success && mode != Execute) { - // Check if we just need to grow the stack. - if (p->fixupStackFault(vaddr)) { - // If we did, lookup the entry for the new page. - success = p->pTable->lookup(vaddr, newEntry); + if (FullSystem) { + Fault fault = walker->start(tc, translation, req, mode); + if (timing || fault != NoFault) { + // This gets ignored in atomic mode. + delayedResponse = true; + return fault; } - } - if (!success) { - return new PageFault(vaddr, true, mode, true, false); + entry = lookup(vaddr); + assert(entry); } else { - Addr alignedVaddr = p->pTable->pageAlign(vaddr); - DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr, - newEntry.pageStart()); - entry = insert(alignedVaddr, newEntry); - } - DPRINTF(TLB, "Miss was serviced.\n"); +#if !FULL_SYSTEM + DPRINTF(TLB, "Handling a TLB miss for " + "address %#x at pc %#x.\n", + vaddr, tc->instAddr()); + + Process *p = tc->getProcessPtr(); + TlbEntry newEntry; + bool success = p->pTable->lookup(vaddr, newEntry); + if (!success && mode != Execute) { + // Check if we just need to grow the stack. + if (p->fixupStackFault(vaddr)) { + // If we did, lookup the entry for the new page. + success = p->pTable->lookup(vaddr, newEntry); + } + } + if (!success) { + return new PageFault(vaddr, true, mode, true, false); + } else { + Addr alignedVaddr = p->pTable->pageAlign(vaddr); + DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr, + newEntry.pageStart()); + entry = insert(alignedVaddr, newEntry); + } + DPRINTF(TLB, "Miss was serviced.\n"); #endif + } } // Do paging protection checks. bool inUser = (m5Reg.cpl == 3 && diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh index e4ea0e1b7..e82784900 100644 --- a/src/arch/x86/tlb.hh +++ b/src/arch/x86/tlb.hh @@ -85,15 +85,11 @@ namespace X86ISA EntryList::iterator lookupIt(Addr va, bool update_lru = true); -#if FULL_SYSTEM - protected: - Walker * walker; + public: Walker *getWalker(); -#endif - public: void invalidateAll(); void invalidateNonGlobal(); diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index 6640f3cea..430356004 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -140,7 +140,8 @@ class BaseCPU(MemObject): tracer = Param.InstTracer(default_tracer, "Instruction tracer") _cached_ports = [] - if buildEnv['TARGET_ISA'] in ['x86', 'arm'] and buildEnv['FULL_SYSTEM']: + if buildEnv['TARGET_ISA'] == 'x86' or \ + (buildEnv['TARGET_ISA'] == 'arm' and buildEnv['FULL_SYSTEM']): _cached_ports = ["itb.walker.port", "dtb.walker.port"] _uncached_ports = [] -- 2.30.2