From 8ae0de5621120b16295fe6b73ca044d4c576af6d Mon Sep 17 00:00:00 2001 From: Andrew Stubbs Date: Thu, 10 Sep 2020 10:10:32 +0100 Subject: [PATCH] amdgcn: align TImode registers This prevents execution failures caused by partially overlapping input and output registers. This is the same solution already used for DImode. gcc/ChangeLog: * config/gcn/gcn.c (gcn_hard_regno_mode_ok): Align TImode registers. * config/gcn/gcn.md: Assert that TImode registers do not early clobber. --- gcc/config/gcn/gcn.c | 3 ++- gcc/config/gcn/gcn.md | 2 ++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/gcc/config/gcn/gcn.c b/gcc/config/gcn/gcn.c index 8b3c4544dd5..84d1fd9a354 100644 --- a/gcc/config/gcn/gcn.c +++ b/gcc/config/gcn/gcn.c @@ -475,7 +475,8 @@ gcn_hard_regno_mode_ok (unsigned int regno, machine_mode mode) return (vgpr_1reg_mode_p (mode) || (!((regno - FIRST_VGPR_REG) & 1) && vgpr_2reg_mode_p (mode)) /* TImode is used by DImode compare_and_swap. */ - || mode == TImode); + || (mode == TImode + && !((regno - FIRST_VGPR_REG) & 3))); return false; } diff --git a/gcc/config/gcn/gcn.md b/gcc/config/gcn/gcn.md index aeb25fbb931..0e73fea93cf 100644 --- a/gcc/config/gcn/gcn.md +++ b/gcc/config/gcn/gcn.md @@ -677,6 +677,8 @@ (set (match_dup 4) (match_dup 5)) (set (match_dup 6) (match_dup 7))] { + gcc_assert (rtx_equal_p (operands[0], operands[1]) + || !reg_overlap_mentioned_p (operands[0], operands[1])); operands[6] = gcn_operand_part (TImode, operands[0], 3); operands[7] = gcn_operand_part (TImode, operands[1], 3); operands[4] = gcn_operand_part (TImode, operands[0], 2); -- 2.30.2