From 8b22ef6af9e6e834600a2e1af844d0309774f610 Mon Sep 17 00:00:00 2001 From: Claudiu Zissulescu Date: Tue, 25 Apr 2017 14:04:25 +0200 Subject: [PATCH] [ARC] Use ACCL, ACCH registers whenever they are available. gcc/ 2017-04-25 Claudiu Zissulescu * config/arc/arc.c (arc_conditional_register_usage): Use ACCL, ACCH registers whenever they are available. From-SVN: r247199 --- gcc/ChangeLog | 5 +++++ gcc/config/arc/arc.c | 9 +++++++++ 2 files changed, 14 insertions(+) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index e55c5df7fd1..5faeb0e79b8 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2017-04-25 Claudiu Zissulescu + + * config/arc/arc.c (arc_conditional_register_usage): Use ACCL, + ACCH registers whenever they are available. + 2017-04-25 Claudiu Zissulescu * config/arc/arc.c (arc_conditional_register_usage): Make D0, D1 diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c index dc201ee7450..0c6b96fcd16 100644 --- a/gcc/config/arc/arc.c +++ b/gcc/config/arc/arc.c @@ -1585,6 +1585,15 @@ arc_conditional_register_usage (void) SET_HARD_REG_BIT (reg_class_contents[WRITABLE_CORE_REGS], ACCH_REGNO); SET_HARD_REG_BIT (reg_class_contents[CHEAP_CORE_REGS], ACCL_REGNO); SET_HARD_REG_BIT (reg_class_contents[CHEAP_CORE_REGS], ACCH_REGNO); + SET_HARD_REG_BIT (reg_class_contents[GENERAL_REGS], ACCL_REGNO); + SET_HARD_REG_BIT (reg_class_contents[GENERAL_REGS], ACCH_REGNO); + SET_HARD_REG_BIT (reg_class_contents[MPY_WRITABLE_CORE_REGS], ACCL_REGNO); + SET_HARD_REG_BIT (reg_class_contents[MPY_WRITABLE_CORE_REGS], ACCH_REGNO); + + /* Allow the compiler to freely use them. */ + fixed_regs[ACCL_REGNO] = 0; + fixed_regs[ACCH_REGNO] = 0; + arc_hard_regno_mode_ok[ACC_REG_FIRST] = D_MODES; } } -- 2.30.2