From 8b38daf4ee6e066dc16b433b89b3566b32b67c92 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 13 Aug 2019 11:53:12 +0100 Subject: [PATCH] add swizzle description to abridged sv spec --- simple_v_extension/abridged_spec.mdwn | 17 +++++++++++++++++ simple_v_extension/vblock_format_table.mdwn | 4 ++-- 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/simple_v_extension/abridged_spec.mdwn b/simple_v_extension/abridged_spec.mdwn index f5a607ab5..86c10714c 100644 --- a/simple_v_extension/abridged_spec.mdwn +++ b/simple_v_extension/abridged_spec.mdwn @@ -221,6 +221,23 @@ Pseudocode for predication: [[!inline raw="yes" pages="simple_v_extension/pred_table" ]] [[!inline raw="yes" pages="simple_v_extension/get_pred_value" ]] +## Swizzle Table + ## Fail-on-First Mode ffirst is a special data-dependent predicate mode. There are two diff --git a/simple_v_extension/vblock_format_table.mdwn b/simple_v_extension/vblock_format_table.mdwn index d10a5e632..6698059c8 100644 --- a/simple_v_extension/vblock_format_table.mdwn +++ b/simple_v_extension/vblock_format_table.mdwn @@ -24,11 +24,11 @@ The VL/MAXVL/SubVL Block format, when 16xil != 0b111, is: """]] When 16xil is 0b111, this is the "Extended" Format, using the >= 192-bit -RISC-V ISA format. Note that the length is 80+16\*nnnnnn, not 192+ +RISC-V ISA format. Note that the length is 96+16\*nnnnnn, not 192+ | base+5 ... base+3 | base+1 | base | no. of bits | | ------ ----------------- | | ---------------- | ------------- | -| ..xxxx xxxxxxxxxxxxxxxx | | x111xxxxx1111111 | 80+16\*nnnnnn | +| ..xxxx xxxxxxxxxxxxxxxx | | x111xxxxx1111111 | 96+16\*nnnnnn | | {ops}{Pred}{Reg}{VL Block}| VBLOCK2 | VBLOCK Prefix | | VBLOCK2 extends the VBLOCK fields: -- 2.30.2