From 8b4796a367ec21d294f7318343e5bb9d7e07a53e Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 26 Feb 2008 23:38:51 -0500 Subject: [PATCH] TLB: Make a TLB base class and put a virtual demapPage function in it. --HG-- extra : convert_revision : cc0e62a5a337fd5bf332ad33bed61c0d505a936f --- src/arch/alpha/tlb.cc | 2 +- src/arch/alpha/tlb.hh | 10 ++++++++-- src/arch/mips/tlb.cc | 2 +- src/arch/mips/tlb.hh | 6 +++++- src/arch/sparc/tlb.cc | 2 +- src/arch/sparc/tlb.hh | 9 +++++++-- src/arch/x86/tlb.cc | 4 ++-- src/arch/x86/tlb.hh | 5 +++-- src/cpu/base_dyn_inst.hh | 13 +++++++++++++ src/cpu/checker/cpu.hh | 16 ++++++++++++++++ src/cpu/o3/cpu.hh | 16 ++++++++++++++++ src/cpu/ozone/cpu.hh | 16 ++++++++++++++++ src/cpu/simple/base.hh | 15 +++++++++++++++ src/cpu/simple_thread.hh | 16 ++++++++++++++++ src/sim/tlb.cc | 6 ++++++ src/sim/tlb.hh | 16 ++++++++++++++-- 16 files changed, 140 insertions(+), 14 deletions(-) diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc index 2e974effe..77bf5e285 100644 --- a/src/arch/alpha/tlb.cc +++ b/src/arch/alpha/tlb.cc @@ -58,7 +58,7 @@ bool uncacheBit40 = false; #define MODE2MASK(X) (1 << (X)) TLB::TLB(const Params *p) - : SimObject(p), size(p->size), nlu(0) + : BaseTLB(p), size(p->size), nlu(0) { table = new TlbEntry[size]; memset(table, 0, sizeof(TlbEntry[size])); diff --git a/src/arch/alpha/tlb.hh b/src/arch/alpha/tlb.hh index 69a33f32d..e61ae5c6d 100644 --- a/src/arch/alpha/tlb.hh +++ b/src/arch/alpha/tlb.hh @@ -44,7 +44,7 @@ #include "params/AlphaDTB.hh" #include "params/AlphaITB.hh" #include "sim/faults.hh" -#include "sim/sim_object.hh" +#include "sim/tlb.hh" class ThreadContext; @@ -52,7 +52,7 @@ namespace AlphaISA { class TlbEntry; - class TLB : public SimObject + class TLB : public BaseTLB { protected: typedef std::multimap PageTable; @@ -79,6 +79,12 @@ namespace AlphaISA void flushProcesses(); void flushAddr(Addr addr, uint8_t asn); + void demapPage(Addr vaddr, uint64_t asn) + { + assert(asn < (1 << 8)); + flushAddr(vaddr, asn); + } + // static helper functions... really EV5 VM traits static bool validVirtualAddress(Addr vaddr) { // unimplemented bits must be all 0 or all 1 diff --git a/src/arch/mips/tlb.cc b/src/arch/mips/tlb.cc index 4923e3e3a..d78aefab4 100644 --- a/src/arch/mips/tlb.cc +++ b/src/arch/mips/tlb.cc @@ -62,7 +62,7 @@ using namespace MipsISA; #define MODE2MASK(X) (1 << (X)) TLB::TLB(const Params *p) - : SimObject(p), size(p->size), nlu(0) + : BaseTLB(p), size(p->size), nlu(0) { table = new MipsISA::PTE[size]; memset(table, 0, sizeof(MipsISA::PTE[size])); diff --git a/src/arch/mips/tlb.hh b/src/arch/mips/tlb.hh index d6f9ac101..4333777ff 100644 --- a/src/arch/mips/tlb.hh +++ b/src/arch/mips/tlb.hh @@ -80,7 +80,7 @@ struct TlbEntry }; -class TLB : public SimObject +class TLB : public BaseTLB { protected: typedef std::multimap PageTable; @@ -120,6 +120,10 @@ class TLB : public SimObject void insert(Addr vaddr, MipsISA::PTE &pte); void insertAt(MipsISA::PTE &pte, unsigned Index, int _smallPages); void flushAll(); + void demapPage(Addr vaddr, uint64_t asn) + { + panic("demapPage unimplemented.\n"); + } // static helper functions... really static bool validVirtualAddress(Addr vaddr); diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc index 740da37ab..22df44908 100644 --- a/src/arch/sparc/tlb.cc +++ b/src/arch/sparc/tlb.cc @@ -46,7 +46,7 @@ namespace SparcISA { TLB::TLB(const Params *p) - : SimObject(p), size(p->size), usedEntries(0), lastReplaced(0), + : BaseTLB(p), size(p->size), usedEntries(0), lastReplaced(0), cacheValid(false) { // To make this work you'll have to change the hypervisor and OS diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh index b38ee15dc..2f7d08320 100644 --- a/src/arch/sparc/tlb.hh +++ b/src/arch/sparc/tlb.hh @@ -39,7 +39,7 @@ #include "params/SparcDTB.hh" #include "params/SparcITB.hh" #include "sim/faults.hh" -#include "sim/sim_object.hh" +#include "sim/tlb.hh" class ThreadContext; class Packet; @@ -47,7 +47,7 @@ class Packet; namespace SparcISA { -class TLB : public SimObject +class TLB : public BaseTLB { #if !FULL_SYSTEM //These faults need to be able to populate the tlb in SE mode. @@ -152,6 +152,11 @@ class TLB : public SimObject typedef SparcTLBParams Params; TLB(const Params *p); + void demapPage(Addr vaddr, uint64_t asn) + { + panic("demapPage(Addr) is not implemented.\n"); + } + void dumpAll(); // Checkpointing diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc index acac3081a..208dec177 100644 --- a/src/arch/x86/tlb.cc +++ b/src/arch/x86/tlb.cc @@ -76,7 +76,7 @@ namespace X86ISA { -TLB::TLB(const Params *p) : SimObject(p), configAddress(0), size(p->size) +TLB::TLB(const Params *p) : BaseTLB(p), configAddress(0), size(p->size) { tlb = new TlbEntry[size]; std::memset(tlb, 0, sizeof(TlbEntry) * size); @@ -169,7 +169,7 @@ TLB::invalidateNonGlobal() } void -TLB::demapPage(Addr va) +TLB::demapPage(Addr va, uint64_t asn) { } diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh index d08d6fa68..f6ccd5731 100644 --- a/src/arch/x86/tlb.hh +++ b/src/arch/x86/tlb.hh @@ -70,6 +70,7 @@ #include "params/X86DTB.hh" #include "params/X86ITB.hh" #include "sim/faults.hh" +#include "sim/tlb.hh" #include "sim/sim_object.hh" class ThreadContext; @@ -83,7 +84,7 @@ namespace X86ISA class TLB; - class TLB : public SimObject + class TLB : public BaseTLB { protected: friend class FakeITLBFault; @@ -120,7 +121,7 @@ namespace X86ISA void invalidateNonGlobal(); - void demapPage(Addr va); + void demapPage(Addr va, uint64_t asn); protected: int size; diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh index 74b250207..bea680fac 100644 --- a/src/cpu/base_dyn_inst.hh +++ b/src/cpu/base_dyn_inst.hh @@ -92,6 +92,19 @@ class BaseDynInst : public FastAlloc, public RefCounted /** InstRecord that tracks this instructions. */ Trace::InstRecord *traceData; + void demapPage(Addr vaddr, uint64_t asn) + { + cpu->demapPage(vaddr, asn); + } + void demapInstPage(Addr vaddr, uint64_t asn) + { + cpu->demapPage(vaddr, asn); + } + void demapDataPage(Addr vaddr, uint64_t asn) + { + cpu->demapPage(vaddr, asn); + } + /** * Does a read to a given address. * @param addr The address to read. diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh index 7b3628986..35dc59ff4 100644 --- a/src/cpu/checker/cpu.hh +++ b/src/cpu/checker/cpu.hh @@ -324,6 +324,22 @@ class CheckerCPU : public BaseCPU void recordPCChange(uint64_t val) { changedPC = true; newPC = val; } void recordNextPCChange(uint64_t val) { changedNextPC = true; } + void demapPage(Addr vaddr, uint64_t asn) + { + this->itb->demapPage(vaddr, asn); + this->dtb->demapPage(vaddr, asn); + } + + void demapInstPage(Addr vaddr, uint64_t asn) + { + this->itb->demapPage(vaddr, asn); + } + + void demapDataPage(Addr vaddr, uint64_t asn) + { + this->dtb->demapPage(vaddr, asn); + } + bool translateInstReq(Request *req); void translateDataWriteReq(Request *req); void translateDataReadReq(Request *req); diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index e902968c1..61d7dcf22 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -263,6 +263,22 @@ class FullO3CPU : public BaseO3CPU /** Registers statistics. */ void fullCPURegStats(); + void demapPage(Addr vaddr, uint64_t asn) + { + this->itb->demapPage(vaddr, asn); + this->dtb->demapPage(vaddr, asn); + } + + void demapInstPage(Addr vaddr, uint64_t asn) + { + this->itb->demapPage(vaddr, asn); + } + + void demapDataPage(Addr vaddr, uint64_t asn) + { + this->dtb->demapPage(vaddr, asn); + } + /** Translates instruction requestion. */ Fault translateInstReq(RequestPtr &req, Thread *thread) { diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh index 61abae807..b0ea2cba9 100644 --- a/src/cpu/ozone/cpu.hh +++ b/src/cpu/ozone/cpu.hh @@ -423,6 +423,22 @@ class OzoneCPU : public BaseCPU virtual void serialize(std::ostream &os); virtual void unserialize(Checkpoint *cp, const std::string §ion); + void demapPage(Addr vaddr, uint64_t asn) + { + itb->demap(vaddr, asn); + dtb->demap(vaddr, asn); + } + + void demapInstPage(Addr vaddr, uint64_t asn) + { + itb->demap(vaddr, asn); + } + + void demapDataPage(Addr vaddr, uint64_t asn) + { + dtb->demap(vaddr, asn); + } + #if FULL_SYSTEM /** Translates instruction requestion. */ Fault translateInstReq(RequestPtr &req, OzoneThreadState *thread) diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh index 8c162a846..918965fdb 100644 --- a/src/cpu/simple/base.hh +++ b/src/cpu/simple/base.hh @@ -367,6 +367,21 @@ class BaseSimpleCPU : public BaseCPU return thread->setMiscReg(reg_idx, val); } + void demapPage(Addr vaddr, uint64_t asn) + { + thread->demapPage(vaddr, asn); + } + + void demapInstPage(Addr vaddr, uint64_t asn) + { + thread->demapInstPage(vaddr, asn); + } + + void demapDataPage(Addr vaddr, uint64_t asn) + { + thread->demapDataPage(vaddr, asn); + } + unsigned readStCondFailures() { return thread->readStCondFailures(); } diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh index 2b79c9708..fa80a283a 100644 --- a/src/cpu/simple_thread.hh +++ b/src/cpu/simple_thread.hh @@ -163,6 +163,22 @@ class SimpleThread : public ThreadState return dtb->translate(req, tc, true); } + void demapPage(Addr vaddr, uint64_t asn) + { + itb->demapPage(vaddr, asn); + dtb->demapPage(vaddr, asn); + } + + void demapInstPage(Addr vaddr, uint64_t asn) + { + itb->demapPage(vaddr, asn); + } + + void demapDataPage(Addr vaddr, uint64_t asn) + { + dtb->demapPage(vaddr, asn); + } + #if FULL_SYSTEM int getInstAsid() { return regs.instAsid(); } int getDataAsid() { return regs.dataAsid(); } diff --git a/src/sim/tlb.cc b/src/sim/tlb.cc index de6779839..7292a69e0 100644 --- a/src/sim/tlb.cc +++ b/src/sim/tlb.cc @@ -48,3 +48,9 @@ GenericTLB::translate(RequestPtr req, ThreadContext * tc, bool) return NoFault; #endif } + +void +GenericTLB::demapPage(Addr vaddr, uint64_t asn) +{ + warn("Demapping pages in the generic TLB is unnecessary.\n"); +} diff --git a/src/sim/tlb.hh b/src/sim/tlb.hh index b5e341185..011cc1144 100644 --- a/src/sim/tlb.hh +++ b/src/sim/tlb.hh @@ -39,13 +39,25 @@ class ThreadContext; class Packet; -class GenericTLB : public SimObject +class BaseTLB : public SimObject { protected: - GenericTLB(const Params *p) : SimObject(p) + BaseTLB(const Params *p) : SimObject(p) {} public: + virtual void demapPage(Addr vaddr, uint64_t asn) = 0; +}; + +class GenericTLB : public BaseTLB +{ + protected: + GenericTLB(const Params *p) : BaseTLB(p) + {} + + public: + void demapPage(Addr vaddr, uint64_t asn); + Fault translate(RequestPtr req, ThreadContext *tc, bool=false); }; -- 2.30.2