From 8b5190aba09f9f1af9f655b543faee2b58f746ef Mon Sep 17 00:00:00 2001 From: Alan Lawrence Date: Fri, 8 May 2015 11:49:02 +0000 Subject: [PATCH] [AArch64] Add vcond(u?)didi pattern * config/aarch64/aarch64-simd.md (aarch64_vcond_internal, vcond, vcondu): Add DImode variant. From-SVN: r222908 --- gcc/ChangeLog | 5 +++++ gcc/config/aarch64/aarch64-simd.md | 36 +++++++++++++++--------------- 2 files changed, 23 insertions(+), 18 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 1d3b0a976c5..87a75d1398e 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2015-05-08 Alan Lawrence + + * config/aarch64/aarch64-simd.md (aarch64_vcond_internal, + vcond, vcondu): Add DImode variant. + 2015-05-08 Alan Lawrence * optabs.c (vector_compare_rtx): Handle RTL operands having VOIDmode. diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 5342c3d20d2..b90f93841f8 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -2057,13 +2057,13 @@ }) (define_expand "aarch64_vcond_internal" - [(set (match_operand:VDQ_I 0 "register_operand") - (if_then_else:VDQ_I + [(set (match_operand:VSDQ_I_DI 0 "register_operand") + (if_then_else:VSDQ_I_DI (match_operator 3 "comparison_operator" - [(match_operand:VDQ_I 4 "register_operand") - (match_operand:VDQ_I 5 "nonmemory_operand")]) - (match_operand:VDQ_I 1 "nonmemory_operand") - (match_operand:VDQ_I 2 "nonmemory_operand")))] + [(match_operand:VSDQ_I_DI 4 "register_operand") + (match_operand:VSDQ_I_DI 5 "nonmemory_operand")]) + (match_operand:VSDQ_I_DI 1 "nonmemory_operand") + (match_operand:VSDQ_I_DI 2 "nonmemory_operand")))] "TARGET_SIMD" { rtx op1 = operands[1]; @@ -2365,13 +2365,13 @@ }) (define_expand "vcond" - [(set (match_operand:VALL 0 "register_operand") - (if_then_else:VALL + [(set (match_operand:VALLDI 0 "register_operand") + (if_then_else:VALLDI (match_operator 3 "comparison_operator" - [(match_operand:VALL 4 "register_operand") - (match_operand:VALL 5 "nonmemory_operand")]) - (match_operand:VALL 1 "nonmemory_operand") - (match_operand:VALL 2 "nonmemory_operand")))] + [(match_operand:VALLDI 4 "register_operand") + (match_operand:VALLDI 5 "nonmemory_operand")]) + (match_operand:VALLDI 1 "nonmemory_operand") + (match_operand:VALLDI 2 "nonmemory_operand")))] "TARGET_SIMD" { emit_insn (gen_aarch64_vcond_internal (operands[0], operands[1], @@ -2398,13 +2398,13 @@ }) (define_expand "vcondu" - [(set (match_operand:VDQ_I 0 "register_operand") - (if_then_else:VDQ_I + [(set (match_operand:VSDQ_I_DI 0 "register_operand") + (if_then_else:VSDQ_I_DI (match_operator 3 "comparison_operator" - [(match_operand:VDQ_I 4 "register_operand") - (match_operand:VDQ_I 5 "nonmemory_operand")]) - (match_operand:VDQ_I 1 "nonmemory_operand") - (match_operand:VDQ_I 2 "nonmemory_operand")))] + [(match_operand:VSDQ_I_DI 4 "register_operand") + (match_operand:VSDQ_I_DI 5 "nonmemory_operand")]) + (match_operand:VSDQ_I_DI 1 "nonmemory_operand") + (match_operand:VSDQ_I_DI 2 "nonmemory_operand")))] "TARGET_SIMD" { emit_insn (gen_aarch64_vcond_internal (operands[0], operands[1], -- 2.30.2