From 8b58b42c6ac11f82d7b7ba8c3ce15d83beb25775 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 8 May 2019 08:23:57 +0100 Subject: [PATCH] whoops connect enable / data correct way round in regfilearray --- src/regfile/regfile.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/regfile/regfile.py b/src/regfile/regfile.py index d898c578..3cb5ef45 100644 --- a/src/regfile/regfile.py +++ b/src/regfile/regfile.py @@ -120,13 +120,13 @@ class RegFileArray(Elaboratable): for (regs, p) in self._rdports: #print (p) - m.d.comb += p.ren.eq(self._get_en_sig(regs, 'ren')) + m.d.comb += self._get_en_sig(regs, 'ren').eq(p.ren) ror = treereduce(list(regs)) m.d.comb += p.data_o.eq(ror) for (regs, p) in self._wrports: - m.d.comb += p.wen.eq(self._get_en_sig(regs, 'wen')) + m.d.comb += self._get_en_sig(regs, 'wen').eq(p.wen) for r in regs: - m.d.comb += p.data_i.eq(r.data_i) + m.d.comb += r.data_i.eq(p.data_i) return m -- 2.30.2