From 8b5cc345538ae1138dab8c405c9c91c2f986113c Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 11 Feb 2020 17:44:24 +0100 Subject: [PATCH] targets/EthernetSoC: be sure memory region is added before adding Wishbone Slave (required by new SoC) --- litex/boards/targets/arty.py | 2 +- litex/boards/targets/genesys2.py | 2 +- litex/boards/targets/kc705.py | 2 +- litex/boards/targets/netv2.py | 2 +- litex/boards/targets/nexys4ddr.py | 2 +- litex/boards/targets/nexys_video.py | 2 +- litex/boards/targets/simple.py | 2 +- litex/boards/targets/versa_ecp5.py | 2 +- 8 files changed, 8 insertions(+), 8 deletions(-) diff --git a/litex/boards/targets/arty.py b/litex/boards/targets/arty.py index 8bbfa3cd..8b0840e4 100755 --- a/litex/boards/targets/arty.py +++ b/litex/boards/targets/arty.py @@ -95,7 +95,7 @@ class EthernetSoC(BaseSoC): interface = "wishbone", endianness = self.cpu.endianness) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") - self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000) + self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac") # timing constraints diff --git a/litex/boards/targets/genesys2.py b/litex/boards/targets/genesys2.py index 55cc272a..583176cd 100755 --- a/litex/boards/targets/genesys2.py +++ b/litex/boards/targets/genesys2.py @@ -88,7 +88,7 @@ class EthernetSoC(BaseSoC): interface = "wishbone", endianness = self.cpu.endianness) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") - self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000) + self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac") # timing constraints diff --git a/litex/boards/targets/kc705.py b/litex/boards/targets/kc705.py index 70b2f9fb..67cdf274 100755 --- a/litex/boards/targets/kc705.py +++ b/litex/boards/targets/kc705.py @@ -89,7 +89,7 @@ class EthernetSoC(BaseSoC): interface = "wishbone", endianness = self.cpu.endianness) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") - self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000) + self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac") # timing constraints diff --git a/litex/boards/targets/netv2.py b/litex/boards/targets/netv2.py index 40e20071..fb6e150f 100755 --- a/litex/boards/targets/netv2.py +++ b/litex/boards/targets/netv2.py @@ -91,7 +91,7 @@ class EthernetSoC(BaseSoC): interface = "wishbone", endianness = self.cpu.endianness) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") - self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000) + self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac") # timing constraints diff --git a/litex/boards/targets/nexys4ddr.py b/litex/boards/targets/nexys4ddr.py index fa78b9d5..79eaa6d0 100755 --- a/litex/boards/targets/nexys4ddr.py +++ b/litex/boards/targets/nexys4ddr.py @@ -90,7 +90,7 @@ class EthernetSoC(BaseSoC): interface = "wishbone", endianness = self.cpu.endianness) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") - self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000) + self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac") # timing constraints diff --git a/litex/boards/targets/nexys_video.py b/litex/boards/targets/nexys_video.py index 4d261d3c..19df6338 100755 --- a/litex/boards/targets/nexys_video.py +++ b/litex/boards/targets/nexys_video.py @@ -90,7 +90,7 @@ class EthernetSoC(BaseSoC): interface = "wishbone", endianness = self.cpu.endianness) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") - self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000) + self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac") # timing constraints diff --git a/litex/boards/targets/simple.py b/litex/boards/targets/simple.py index 904959ed..7250c98f 100755 --- a/litex/boards/targets/simple.py +++ b/litex/boards/targets/simple.py @@ -49,7 +49,7 @@ class EthernetSoC(BaseSoC): self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness, with_preamble_crc=False) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") - self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000) + self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac") diff --git a/litex/boards/targets/versa_ecp5.py b/litex/boards/targets/versa_ecp5.py index 9951b798..2ee57a20 100755 --- a/litex/boards/targets/versa_ecp5.py +++ b/litex/boards/targets/versa_ecp5.py @@ -115,7 +115,7 @@ class EthernetSoC(BaseSoC): self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") - self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000) + self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac") # timing constraints -- 2.30.2