From 8b5da9c62310cbc8fc84591ed50d1eaaf1df7a6a Mon Sep 17 00:00:00 2001 From: Jan Kowalewski Date: Fri, 18 Oct 2019 09:33:31 +0200 Subject: [PATCH] cores/icap/ICAPBitstream: add source ready signal. --- litex/soc/cores/icap.py | 1 + 1 file changed, 1 insertion(+) diff --git a/litex/soc/cores/icap.py b/litex/soc/cores/icap.py index 73319925..6c312dda 100644 --- a/litex/soc/cores/icap.py +++ b/litex/soc/cores/icap.py @@ -114,6 +114,7 @@ class ICAPBitstream(Module, AutoCSR): self.comb += [ If(fifo.source.valid, _csib.eq(0), + fifo.source.ready.eq(1), _i.eq(fifo.source.data) ) ] -- 2.30.2