From 8b61548424df3c7722abcfeb5f0c808d67c3c248 Mon Sep 17 00:00:00 2001 From: Tobias Platen Date: Wed, 20 Jul 2022 21:01:35 +0200 Subject: [PATCH] merge part 2 of Cesar's patch --- src/ls2.py | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/src/ls2.py b/src/ls2.py index 619637b..2e313ce 100644 --- a/src/ls2.py +++ b/src/ls2.py @@ -290,13 +290,17 @@ class DDR3SoC(SoC, Elaboratable): # set up clock request generator pod_bits = 25 sync_bits = 26 + need_bridge=False if fpga in ['versa_ecp5', 'versa_ecp5_85', 'isim', 'ulx3s', - 'orangecrab']: + 'orangecrab', 'rcs_arctic_tern_bmc_card']: if fpga in ['isim']: pod_bits = 5 sync_bits = 6 + if fpga in ['orangecrab', 'rcs_arctic_tern_bmc_card']: + need_bridge=True self.crg = ECP5CRG(clk_freq, dram_clk_freq=dram_clk_freq, - pod_bits=pod_bits, sync_bits=sync_bits) + pod_bits=pod_bits, sync_bits=sync_bits, + need_bridge=need_bridge) if fpga in ['arty_a7']: self.crg = ArtyA7CRG(clk_freq) @@ -960,8 +964,8 @@ def build_platform(fpga, firmware): platform.add_resources(spi_0_ios) spi_0_pins = platform.request("spi_0", 0) - - if platform is not None and \ + orangecrab_enable_spi = False + if orangecrab_enable_spi and platform is not None and \ fpga in ['orangecrab']: # spi_flash_mosi <= spi_sdat_o(0) when spi_sdat_oe(0) = '1' else 'Z'; # spi_flash_miso <= spi_sdat_o(1) when spi_sdat_oe(1) = '1' else 'Z'; @@ -1102,9 +1106,9 @@ def build_platform(fpga, firmware): if toolchain == 'Trellis': # add -abc9 option to yosys synth_ecp5 - #os.environ['NMIGEN_synth_opts'] = '-abc9 -nowidelut' - #os.environ['NMIGEN_synth_opts'] = '-abc9' - os.environ['NMIGEN_synth_opts'] = '-nowidelut' + os.environ['NMIGEN_synth_opts'] = '-abc9' # optimize for speed + # os.environ['NMIGEN_synth_opts'] = '-nowidelut' # optimize for size + # os.environ['NMIGEN_synth_opts'] = '-abc9 -nowidelut' # conflicting goals if toolchain == 'yosys_nextpnr': # add --seed 2 to arty a7 compile-time options -- 2.30.2